| Patent application number | Description | Published |
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| 20090011204 | CARBON NANOSTRUCTURES AND METHODS OF MAKING AND USING THE SAME - Carbon nanoflakes, methods of making the nanoflakes, and applications of the carbon nanoflakes are provided. In some embodiments, the carbon nanoflakes are carbon nanosheets, which are less than 2 nm thick. The carbon nanoflakes may be made using RF-PECVD. Carbon nanoflakes may be useful as field emitters, for hydrogen storage applications, for sensors, and as catalyst supports. | 01-08-2009 |
| 20090011241 | Carbon Nanoflake Compositions and Methods of Production - Novel compositions and morphologies of carbon nanoflakes are described, as well as methods for making carbon nanoflakes using a radio frequency plasma enhanced chemical vapor deposition (RF-PECVD) process. Acetylene is used as a CVD source gas. By utilizing high concentrations of acetylene in the CVD source gas at relatively low temperatures, carbon nanoflake growth rate and robustness are improved, and the resulting carbon nanoflakes have enhanced height uniformity. | 01-08-2009 |
| 20090071371 | Silicon Oxynitride Coating Compositions - Silicon oxynitride compositions are described herein. These compositions are typically deposited onto substrates using a nitrogen plasma-based, reactive sputtering method. Depending on their composition, these coatings can be used for field emission suppression, dielectric applications, reflection control, and surface passivation. | 03-19-2009 |
| 20090277782 | Silicon Oxynitride Coating Compositions - Silicon oxynitride compositions are described herein. These compositions are typically deposited onto substrates using a nitrogen plasma-based, reactive sputtering method. Depending on their composition, these coatings can be used for field emission suppression, dielectric applications, reflection control, and surface passivation. | 11-12-2009 |
| 20110175038 | COATED CARBON NANOFLAKES - Compositions of carbon nanoflakes are coated with a low Z compound, where an effective electron emission of the carbon nanoflakes coated with the low Z compound is improved compared to an effective electron emission of the same carbon nanoflakes that are not coated with the low Z compound or of the low Z compound that is not coated onto the carbon nanoflakes. Compositions of chromium oxide and molybdenum carbide-coated carbon nanoflakes are also described, as well as applications of these compositions. Carbon nanoflakes are formed and a low Z compound coating, such as a chromium oxide or molybdenum carbide coating, is formed on the surfaces of carbon nanoflakes. The coated carbon nanoflakes have excellent field emission properties. | 07-21-2011 |
| 20120198761 | APPARATUS AND METHOD FOR PRODUCING AND HARVESTING ALGAE - An apparatus and method are described for producing and harvesting algae. The orientation of the production substrates is critical for maximizing production as a function of water area utilized. By employing an array of algae production substrates in a vertical configuration relative to the water surface, the yield of algae production per area of open water is increased substantially relative to prior art algae production systems. | 08-09-2012 |
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| 20100249809 | THREADABLE KNOT SOFT TISSUE DEFECT REPAIR SYSTEM - A soft tissue defect repair system for approximating defects, such as defects in the annulus fibrosus of an intervertebral disc, includes a cannulated rod through which is disposed a suture retrieval device. A strand of suture includes a locking or ratcheting knot pre-tied around the outside of the cannulated rod and a free end that is guided in and out of the soft tissue. A knot pusher fits around the cannulated rod, which is used to push the knot off of the cannulated rod after the stitching of the tissue is accomplished. The defect is approximated by tensioning the free end. Various suturing methods or patterns are disclosed for defect approximation. | 09-30-2010 |
| 20100312280 | ANCHOR-IN-ANCHOR SYSTEM FOR USE IN BONE FIXATION - An anchor-in-anchor fixation system is provided for securing underlying structure, such as bone. The fixation system includes a first bone anchor having a shaft for fixation to underlying bone, and a head that defines an internal bore. A second bone anchor extends through the bore and into underlying bone. A fixation assembly is also provided that includes one or more fixation systems coupled to an auxiliary attachment member configured for long bone fixation, spinal fixation, or fixation of other bones as desired. | 12-09-2010 |
| 20110028998 | BI-DIRECTIONAL SUTURE PASSER - A bi-directional suture passing instrument configured to approach soft tissues perpendicularly, enables safer and more efficient surgical repairs and minimally invasive techniques to be employed, useful in areas such as annulus repair, meniscal repair, shoulder arthroscopy, hernia repair, laproscopic repair, and wound closure. | 02-03-2011 |
| 20110071551 | MULTI-STITCH ANCHOR SUTURE-BASED SOFT TISSUE REPAIR SYSTEM - A soft tissue repair system includes a needle, a sheath, and a actuator. The needle has a body and a tip that extends distally from the body. The body defines a longitudinal channel configured to hold a plurality of suture anchors, and an ejection port proximal to the tip. The needle is configured to receive and hold a strand of suture. The sheath is disposed coaxially around the exterior of the needle, and is translatable with respect to the needle between a first position, and a second position. The actuator is translatable within the needle channel and is configured to push the suture anchors distally such that a first suture anchor of the plurality of suture anchors engages the suture strand held by the needle and sheath. | 03-24-2011 |
| 20110270278 | ANCHOR ASSEMBLY INCLUDING EXPANDABLE ANCHOR - An anchor assembly can include at least one anchor member, such as a pair of anchor members that are configured to be implanted in a target anatomical location in a first configuration, and can subsequently be actuated to an expanded configuration that secures the anchor members in the target anatomy. The anchor assembly can further include a connector member that attaches the pair of anchor members together across a gap so as to approximate the anatomical defect. | 11-03-2011 |
| 20120004669 | INSERTION INSTRUMENT FOR ANCHOR ASSEMBLY - An insertion instrument is configured to eject a pair of anchor bodies across an anatomical gap so as to approximate the gap. The insertion instrument can include a single cannula that retains the pair of anchor bodies in a stacked relationship, or a pair of adjacent cannulas that each retain respective anchor bodies. The insertion instrument can be actuated so as to eject the anchor bodies into respective target anatomical locations. | 01-05-2012 |
| 20120109156 | METHODS FOR APPROXIMATING A TISSUE DEFECT USING AN ANCHOR ASSEMBLY - An insertion instrument is configured to eject one or more of anchor bodies across an anatomical gap so as to approximate the gap. The insertion instrument can include a single cannula that retains the pair of anchor bodies in a stacked relationship, or a pair of adjacent cannulas that each retains respective anchor bodies. The insertion instrument can be actuated so as to eject the anchor bodies into respective target anatomical locations. | 05-03-2012 |
| 20120150223 | STITCH LOCK FOR ATTACHING TWO OR MORE STRUCTURES - An anchor assembly can include at least one anchor member, such as a pair of anchor members that are configured to be implanted in a target anatomical location in a first configuration, and can subsequently be actuated to an expanded configuration that secures the anchor members in the target anatomy. The anchor assembly can further include a connector member configured as a stitch lock that attaches the pair of anchor members together across a gap so as to approximate the anatomical defect. | 06-14-2012 |
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| 20090235097 | Data Center Power Management - An exemplary method for managing power consumption of a data center includes monitoring power consumption of a data center, assessing power consumption with respect to a billing equation for power, based on the assessment, deciding whether to implement a power policy where the power policy reduces instantaneous power consumption by the data center and increases a load factor wherein the load factor is an average power consumed by the data center divided by a peak power consumed by the data center over a period of time. Various other methods, devices, systems, etc., are also disclosed. | 09-17-2009 |
| 20090240798 | Resource Equalization for Inter- and Intra- Data Center Operations - An exemplary component for managing requests for resources in a data center includes a service request module for receiving requests for resources from a plurality of services and a resource module to monitor resources in a data center and to match received requests to resources. Such a component optionally includes an application programming interface (API) that provides for sending information in response to an API call made by a service. Other methods, devices and systems are also disclosed. | 09-24-2009 |
| 20090307094 | Data center programming and application distribution interface - An exemplary data center interface for distributing and monitoring Web applications includes a specification that specifies a call statement to distribute one or more components of a Web application to one or more data centers and a call statement to report metrics associated with performance of the Web application. An exemplary data center interface for associating advertisements with distributed Web applications includes a specification that specifies a call statement and one or more call statement parameters to associate an advertisement with one or more distributed Web applications based on at least one criterion. Various other devices, systems and methods are also described. | 12-10-2009 |
| 20100076933 | TECHNIQUES FOR RESOURCE LOCATION AND MIGRATION ACROSS DATA CENTERS - An exemplary system includes a front-end component to receive requests for resources in a data center and configured to associate each request with identifying information, to locate one or more resources for each request and to store, in a log file, the identifying information and information about the location of the one or more resources; one or more distributed computation and storage components to acquire log file information and configured to analyze log information to decide if one or more resources associated with one or more requests should be migrated to a data center in a different geographical location; and a location service component to receive decisions made by the one or more distributed computation and storage components and configured to inform the front-end component when a decision causes one or more resources to be migrated to a data center in a different geographical location to thereby allow the front-end component to re-direct future requests for the one or more migrated resources to the data center in the different geographical location. Various other devices, systems and methods are also described. | 03-25-2010 |
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| 20110006377 | Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements - Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure. | 01-13-2011 |
| 20110006436 | Conductive Via Plug Formation - Various embodiments of the present invention are generally directed to a method of forming a conductive via plug in a semiconductor device. A first and second metal layer are electrically connected by a via plug that is formed by depositing a tungsten seed layer on a plurality of metal barrier layers within a recess using atomic layer deposition. The recess is then filled with tungsten using chemical vapor deposition. | 01-13-2011 |
| 20110007547 | Vertical Non-Volatile Switch with Punchthrough Access and Method of Fabrication Therefor - A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain. | 01-13-2011 |
| 20110007552 | Active Protection Device for Resistive Random Access Memory (RRAM) Formation - Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level | 01-13-2011 |
| 20110170335 | Vertical Non-Volatile Switch with Punchthrough Access and Method of Fabrication Therefor - A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain. | 07-14-2011 |
| 20120074466 | 3D MEMORY ARRAY WITH VERTICAL TRANSISTOR - A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell. | 03-29-2012 |
| 20120074488 | VERTICAL TRANSISTOR WITH HARDENING IMPLATATION - A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces. | 03-29-2012 |
| 20120080725 | VERTICAL TRANSISTOR MEMORY ARRAY - A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array. | 04-05-2012 |
| 20120199915 | Patterning Embedded Control Lines for Vertically Stacked Semiconductor Elements - The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure. | 08-09-2012 |
| 20130302948 | 3D ARRAY WITH VERTICAL TRANSISTOR - A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell. | 11-14-2013 |
| 20140097400 | VERTICAL TRANSISTOR WITH HARDENING IMPLANTATION - A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces. | 04-10-2014 |
