Patent application number | Description | Published |
20080238390 | Dynamically adjusted multi-phase regulator - In some embodiments, a multi-phase converter with dynamic phase adjustment is provided. | 10-02-2008 |
20100033236 | PACKAGED VOLTAGE REGULATOR AND INDUCTOR ARRAY - Inductors packaged with a voltage regulator for an integrated circuit within the same package are deposited to a sufficient thickness to reduce resistance and improve the quality factor. Furthermore, the voltage regulator switches currents through the inductors at a relatively high frequency such that the overall size and inductances of the inductors may be reduced. As a consequence, integrating both the integrated circuits including a voltage regulator and associated inductor array in a single package is facilitated. Other embodiments are described and claimed. | 02-11-2010 |
20100164477 | HIGH SPEED VOLTAGE REGULATOR WITH INTEGRATED LOSELESS CURRENT SENSING - In general, in one aspect, the disclosure describes a high-speed multi-phase voltage regulator (VR) capable of sensing load current. For each phase leg, the VR includes a current mirror to mirror current in switching elements, a current sense to sense high side current in the current mirror, and a I-V converter to convert the sensed high side current to a voltage. The high side sensed current for each phase leg is averaged and the duty cycle for the VR is extracted. The average high side sensed current and the duty cycle are converted to digital by an A-D converter. Digital circuitry corrects the sensed current by adjusting for the gain and offset voltage of the VR. The adjusted sensed value is divided by the duty cycle to convert to load current and the average load current is multiplied by the number of phases operating to determine overall load current. | 07-01-2010 |
20100164622 | SINGLE-ENDED TO DIFFERENTIAL AMPLIFICATION AND PIPELINE ANALOG-TO-DIGITAL CONVERSION FOR DIGITALLY CONTROLLED DC-DC CONVERTERS - Methods and systems to amplify and convert a single-ended analog signal to a differential signal and to convert the differential signal to a digital value, including to time-multiplex a plurality of windowed single-ended analog error signals, amplify a difference between the time-multiplexed analog signals, sample a corresponding amplified difference signal and an inverted amplified difference signal, amplify and center the samples about a common mode, and convert a corresponding amplified differential signal to digital values in a pipeline fashion. Bias adjustable features may be implemented to control a bandwidth, and clock rates may be adjustable to correspond to the bandwidth. | 07-01-2010 |
20110316339 | DISTRIBUTED POWER DELIVERY SCHEME FOR ON-DIE VOLTAGE SCALING - A high-speed low dropout (HS-LDO) voltage regulation circuit suitable to enable a power gate unit to produce a variable voltage signal based on the load of a processor is disclosed herein. In various embodiments, selection logic may dynamically enable or disable the HS-LDO circuit to allow the power gate unit to operate under a fully-on or fully-off mode. Other embodiments may be disclosed or claimed. | 12-29-2011 |
20130318387 | DISTRIBUTED POWER DELIVERY SCHEME FOR ON-DIE VOLTAGE SCALING - A high-speed low dropout (HS-LDO) voltage regulation circuit suitable to enable a power gate unit to produce a variable voltage signal based on the load of a processor is disclosed herein. In various embodiments, selection logic may dynamically enable or disable the HS-LDO circuit to allow the power gate unit to operate under a fully-on or fully-off mode. Other embodiments may be disclosed or claimed. | 11-28-2013 |
20140019654 | DYNAMIC LINK WIDTH ADJUSTMENT - Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations where PCIe links are almost always active even at very low traffic rates. Embodiments achieve these benefits based on, for example, run-time monitoring of bandwidth requirement for integrated and non-integrated ports located downstream for the PCIe controller. This provides power savings with little impact on performance. Other embodiments are discussed herein. | 01-16-2014 |
20140095944 | METHOD AND APPARATUS FOR OPTIMIZING POWER AND LATENCY ON A LINK - An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link. | 04-03-2014 |