Patent application number | Description | Published |
20080198953 | Decoding Method and Decoding Apparatus - Disclosed herein is a decoding method of performing maximum a posteriori probability (MAP) decoding of selecting one decoded word from one or more decoded word candidates obtained by subjecting a linear code to iterative decoding by comparison of distances between a reception word and each decoded word candidate. A decoded word candidate in which a known value in a part of a transmission word has been changed to another value is excluded from the one or more decoded word candidates. | 08-21-2008 |
20090125780 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals. A symbol interleaver is arranged in operation to read-into a symbol interleaver memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the interleaver memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals. The set of addresses are generated by an address generator which has been optimised to interleave the data symbols on to the sub-carrier signals of the OFDM carrier signals for a given operating mode of the OFDM system, such as a 32K operating mode for DVB-T2 or DVB-C2. | 05-14-2009 |
20090158128 | DECODING DEVICE, DECODING METHOD, RECEIVING DEVICE, AND STORAGE MEDIUM REPRODUCING DEVICE - A decoding device for a linear code on a ring R, the decoding device including: a plurality of storage media; and a processing section; wherein the processing section uses a part of reliability of all symbols at a previous time to update reliability of each symbol in a process of iterative decoding for increasing the reliability of each symbol, and further retains a part used to update retained reliability information and a part unused to update the retained reliability information on two separate storage media. | 06-18-2009 |
20090217122 | Coding Apparatus and Coding Method - The present invention relates to a coding apparatus and a coding method by which the circuit scale can be reduced without changing the operation speed in coding of a linear code. An adder | 08-27-2009 |
20100269019 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer | 10-21-2010 |
20100275100 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD AS WELL AS ENCODING APPARATUS AND ENCODING METHOD - A data processing apparatus, a data processing method, an encoding apparatus, and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of 2/3, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by b | 10-28-2010 |
20100275101 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of data. A demultiplexer replaces, in accordance with an allocation rule for allocating code bits of an LDPC code to symbol bits representative of symbols, mb bits from among the code bits and sets the code bits after the replacement as symbol bits of b symbols. According to the allocation rule, where groups into which the code bits and the symbol bits are to be grouped in response to an error probability thereof are set as code bit groups and symbol bit groups, respectively, a combination of any of the code bit groups and the symbol bit group of the symbol bits to which the code bits of the code bit group are to be allocated and bit numbers of the code bits and the symbols bits are prescribed. | 10-28-2010 |
20100281329 | DATA PROCESSING APPARATUS, DATA PROCESSING METHOD AND PROGRAM - The present invention relates to a data processing apparatus, a data processing method and a program which can improve the tolerance of code bits of an LDPC code to errors. | 11-04-2010 |
20100299572 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD AS WELL AS ENCODING APPARATUS AND ENCODING METHOD - A data processing apparatus, a data processing method, an encoding apparatus and an encoding method which can be applied, for example, to a transmission system for transmitting an LDPC code and so forth, and which can improve the tolerance to errors. Of an LDPC code which is prescribed in the DVB-S.2 and has a code length of 64,800 and an encoding rate of ⅔, mb code bits are replaced, and the code bits after the replacement become symbol bits of b symbols. When m is 8 and b is 2, where the i+1th bit from the most significant bit of 8×2 code bits and 8×2 symbol bits of two successive symbols are represented by b | 11-25-2010 |
20100325512 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of code bits of an LDPC code such as burst errors or erasure. | 12-23-2010 |
20120320994 | ENCODER AND ENCODING METHOD PROVIDING INCREMENTAL REDUNDANCY - The present invention relates to an encoder for error correction code encoding input data words (D) into codewords (Z | 12-20-2012 |
20130117632 | STORAGE CONTROL APPARATUS - Embodiments of the technology disclosed herein are intended to flexibly set the rules of attaching error correction codes to a group of data sequences stored in a memory. A storage control apparatus has an error correction code attachment rule hold block and an error correction portion. The error correction code attachment rule hold block holds the rules of attaching error correction codes to a group of data sequences stored in a memory by relating the rules with the data for each address of the group of data sequences. If an access occurs to the memory, the error correction portion executes error correction processing on a group of data sequences stored in the memory in accordance with the attachment rules related to the address at which the access occurred. | 05-09-2013 |
20130139030 | STORAGE CONTROLLER, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROLLING METHOD - A storage controller includes an error correcting code managing portion, an address managing portion and an error correcting portion. The error correcting code managing portion manages a correspondence relationship between predetermined plural pieces of unit data, and a second error code corresponding to the plural pieces of unit data every entry when plural pieces of unit data and a second error correcting code are stored in a storage portion. The address managing portion manages a correspondence relationship between logical addresses and the entries in the error correcting code managing portion. The error correcting portion acquires the entry in the error correction managing portion corresponding to the logical address as an object of read from the address managing portion, and carries out error correction based on the plural pieces of unit data managed in the entry concerned, and the second error correcting code. | 05-30-2013 |
20130166992 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present invention relates to a data processing device and a data processing method capable of improving the resistance to data error. In a case where an LDPC code having a code length of 4,320 bits is mapped into 16 signal points, when a code bit of 4×2 bits and the (#i+1)-th bit from the most significant bit of symbol bits of 4×2 bits of two consecutive symbols are bits b#i and y#i, a demultiplexer performs an interchange process in which b | 06-27-2013 |
20130227378 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present invention relates to data processing devices and data process methods that can increase tolerance for data errors. | 08-29-2013 |
20130254617 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present invention relates to a data processing device and a data processing method capable of improving the resistance to error of data. An LDPC encoder | 09-26-2013 |
20130290816 | DATA-PROCESSING DEVICE AND DATA-PROCESSING METHOD - The present technology relates to a data-processing device and a data-processing method, which are capable of improving tolerance for an error of data. | 10-31-2013 |
20130297992 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device and a data processing method capable of improving resistance to error of data. An LDPC encoder encodes by an LDPC code whose code length is 16200 bits and code rate is 4/15, 7/15, or 8/15. A parity check matrix of the LDPC code is composed by arrangement of an element of an information matrix determined by a parity check matrix initial value table indicating a position of the element of the information matrix corresponding to an information length corresponding to the code length and the code rate for each 360 columns of the parity check matrix with a period of 360 columns in a column direction. The parity check matrix initial value table is for digital broadcasting for a mobile terminal, for example. This technology may be applied to a case in which LDPC encoding and LDPC decoding are performed. | 11-07-2013 |
20130305113 | DATA-PROCESSING DEVICE AND DATA-PROCESSING METHOD - When an LDPC code having a code length of 16200 bits is mapped to 16 signal points, a demultiplexer performs exchanging such that when a (#i+1)-th bit from a most significant bit of code bits of 4×2 bits and a (#i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of 2 consecutive symbols are represented by a bit b#i and a bit y#i, respectively, for an LDPC codes having coding rates of 7/15, b | 11-14-2013 |
20130311850 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - A data processing device and a data processing method capable of improving resistance to errors. Code bits of an LDPC code with a code length N of 16200 bits is written to, for example, eight storage units. When the code bits are stored in the storage units, a process of changing the storage start position of the code bits for each storage unit is performed as a sorting process of sorting the bits of the LDPC code such that a plurality of code bits corresponding to 1s in an arbitrary row of the parity check matrix of the LDPC code are not included in a single symbol which is read from the storage units. The present technology can be applied to, for example, the transmission of the LDPC code. | 11-21-2013 |
20140040707 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technology relates to a data processing device and a data processing method that enable tolerance against error of data to be improved. In the case in which an LDPC code having a code length of DVB-S.2 of 16200 bits and an encoding rate of 1/3 is modulated by 16 QAM, if a code bit of 4×2 bits and a (i+1)-th bit from a most significant bit of symbol bits of 4×2 bits of two consecutive symbols are set to bits b#i and y#i, a demultiplexer performs interchanging to allocate b0, b1, b2, b3, b4, b5, b6, and b7 to y6, y0, y3, y4, y5, y2, y1, and y7, respectively. The present invention can be applied to a transmission system transmitting an LDPC code or the like. | 02-06-2014 |
20140047295 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technique relates to data processing devices and data processing methods that can increase tolerance for data errors. | 02-13-2014 |
20140082452 | DATA PROCESSING DEVICE AND DATA PROCESSING METHOD - The present technique relates to a data processing device and a data processing method that enable resistance to error of data to be improved. | 03-20-2014 |
20140223256 | ERROR DETECTION AND CORRECTION UNIT, ERROR DETECTION AND CORRECTION METHOD, INFORMATION PROCESSOR, AND PROGRAM - An error detection and correction unit includes: a first-code error detection section configured to detect whether or not each of a plurality of first code words in a second code word has an error, the second code word generated by encoding the plurality of first code words in chains and being a code word containing a plurality of partial data; and a second-code error correction section configured to correct the error in one partial data containing the first code word in which the error is detected of the plurality of partial data in the second code word, based on adjacent partial data adjacent to the one partial data. | 08-07-2014 |
20140301132 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD THEREOF - Provided is a storage control device including a history information holding unit configured to hold history information in a predetermined data area of a memory cell holding either a first value or a second value for each bit, the history information indicating which mode of a first mode or a second mode is employed upon a previous write operation, the first mode setting all bits to the first value and then setting any bit to the second value, the second mode setting all bits to the second value and then setting any bit to the first value, and a bitwise operation unit configured to perform a write operation in the second mode if the history information indicates the first mode and to perform a write operation in the first mode if the history information indicates the second mode. | 10-09-2014 |
20150046765 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 24/30, 25/30, 26/30, 27/30, 28/30, or 29/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding. | 02-12-2015 |
20150046766 | DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - A data processing apparatus and a data processing method which enable provision of an LDPC code that achieves good error-rate performance. An LDPC encoding unit performs encoding using an LDPC code having a code length of 64800 bits and a code rate of 18/30, 19/30, 20/30, 21/30, 22/30, or 23/30. The LDPC code includes information bits and parity bits, and a parity check matrix H is composed of an information matrix portion corresponding to the information bits of the LDPC code, and a parity matrix portion corresponding to the parity bits. The information matrix portion of the parity check matrix H is represented by a parity check matrix initial value table that shows positions of elements of 1 in the information matrix portion in units of 360 columns. The apparatus and method may be applied to LDPC encoding and LDPC decoding. | 02-12-2015 |