| Patent application number | Description | Published |
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| 20090141579 | Power Up/Down Sequence Scheme for Memory Devices - A method for controlling a word line signal for a memory device during a power down process, comprising: pulling the word line signal down to a low logic state; disconnecting a current path from an external power supply to an internal power supply after the word line signal has been pulled down to the low logic state; and disconnecting a current path from an external ground voltage to an internal ground voltage after a current path from an external power supply to an internal power supply has been completely disconnected. | 06-04-2009 |
| 20090285010 | Write Assist Circuit for Improving Write Margins of SRAM Cells - A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines. | 11-19-2009 |
| 20100246311 | CLOCK GENERATORS, MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR PROVIDING AN INTERNAL CLOCK SIGNAL - A clock generator includes a first input end and a second input end. The first input end is capable of receiving a first clock signal including a first state transition and a second state transition defining a first pulse width. The second input end is capable of receiving a second clock signal having a third state transition. A time period ranges from the first state transition to the third state transition. The clock generator can compare the first pulse width and the time period. The clock generator can output a third clock signal having a second pulse width ranging from a fourth state transition to a fifth state transition. The fifth state transition of the third clock signal is capable of being triggered by the second state transition of the first clock signal or the third state transition of the second clock signal depending on the comparison of the first pulse width and the time period. | 09-30-2010 |
| 20120020176 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - Some embodiments regard a circuit comprising: a first left transistor having a first left drain, a first left gate, and a first left source; a second left transistor having a second left drain, a second left gate, and a second left source; a third left transistor having a third left drain, a third left gate, and a third left source; a first right transistor having a first right drain, a first right gate, and a first right source; a second right transistor having a second right drain, a second right gate, and a second right source; a third right transistor having a third right drain, a third right gate, and a third right source; a left node electrically coupling the first left drain, the second left drain, the second left gate, the third right gate, and the third left drain; and a right node electrically coupling the first right drain, the second right drain, the second right gate, the third left gate, and the third right drain. | 01-26-2012 |
| 20130010560 | GENERATING AND AMPLIFYING DIFFERENTIAL SIGNALS - A circuit includes a first node, a second node, a first current mirror circuit, and a second current minor circuit. The first current mirror circuit has a reference end and a mirrored end. The reference end of the first current minor circuit is coupled to the first node, and the mirrored end of the first current minor circuit is coupled to the second node. The second current minor circuit has a reference end and a mirrored end. The reference end of the second current minor circuit is coupled to the second node, and the mirrored end of the second current minor circuit is coupled to the first node. | 01-10-2013 |
| 20130088926 | TRACKING MECHANISMS - A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro. | 04-11-2013 |
| 20130088927 | SYSTEM AND METHOD FOR GENERATING A CLOCK - A first clock is received by a memory macro. In response to a first clock transition of the first clock, a first transition of a second clock and of a third clock is generated. A tracking transition of a tracking signal is caused by the second clock. Based on a later transition of a second clock transition of the first clock and the tracking transition of the tracking signal, a second transition of the third clock is generated. The third clock is for use by an input-output of the memory macro. | 04-11-2013 |
| 20130215693 | TRACKING CAPACITIVE LOADS - A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell. | 08-22-2013 |
| 20140140158 | PRE-CHARGING A DATA LINE - A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver. | 05-22-2014 |
| 20140146629 | VOLTAGE BATTERY - A circuit includes a voltage generating circuit and a voltage keeper circuit. The voltage generating circuit includes a first node. The voltage keeper circuit includes a second node and a third node. The first node is coupled with the second node. The voltage generating circuit is configured to generate a voltage value at the first node and the second node to maintain the third node at a particular third node voltage. | 05-29-2014 |
| 20140177352 | SHARED TRACKING CIRCUIT - A system comprises a plurality of first memory macros and a first tracking circuit to be shared by the plurality of first memory macros. The first tracking circuit includes at least one of a first tracking circuit associated with a row of memory cells of a first memory macro of the plurality of first memory macros, a first tracking circuit associated with a column of memory cells of the first memory macro of the plurality of first memory macros, a first decoder tracking circuit associated with decoding circuitries of the first memory macro of the plurality of first memory macros, and a first input-output tracking circuit associated with input-output circuitries of the first memory macro of the plurality of first memory macros. | 06-26-2014 |
| 20140269026 | TRACKING CIRCUIT - A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal. | 09-18-2014 |
| 20140282318 | TIMING DELAY CHARACTERIZATION METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay. | 09-18-2014 |
| 20140282319 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted. | 09-18-2014 |
| 20150029797 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro comprises a data line, a first interface circuit comprising a first node coupled to the data line, and a voltage keeper configured to control a voltage level at the first node, and a second interface circuit comprising a second node coupled with the data line, wherein the voltage keeper is configured to control a voltage level at the second node via the data line. | 01-29-2015 |
| 20150071016 | TRACKING MECHANISMS - A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated. | 03-12-2015 |
| 20150095867 | SEMICONDUCTOR CIRCUIT DESIGN METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block. | 04-02-2015 |
| 20150138898 | SHARED TRACKING CIRCUIT - A system includes a first plurality of memory macros and a first tracking circuit associated with a memory macro of the first plurality of memory macros. Each memory macro of the first plurality of memory macros includes a corresponding global control circuit configured to receive a first reset signal. The first tracking circuit is configured to generate the first reset signal. | 05-21-2015 |
| 20150162060 | MEMORY MACRO WITH A VOLTAGE KEEPER - A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line. | 06-11-2015 |
| 20150178430 | TIMING DELAY CHARACTERIZATION METHOD, MEMORY COMPILER AND COMPUTER PROGRAM PRODUCT - A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay. The processor is further configured to generate timing delays of the memory circuit based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay. | 06-25-2015 |
| 20150213858 | READING DATA FROM A MEMORY CELL - In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction. | 07-30-2015 |
| 20150294715 | PRE-CHARGING A DATA LINE - A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal. | 10-15-2015 |
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| 20120019151 | AMBIENT LIGHT CALIBRATION FOR ENERGY EFFICIENCY IN DISPLAY SYSTEMS - A method, system, and apparatus that can be used to operate a display device in an energy efficient manner. The energy efficient display device can effectively and efficiently compensate for changes in ambient light incident at a display screen of the display device using an internal ambient light sensor to provide control signals to a backlight driver. | 01-26-2012 |
| 20120019494 | ALIGNMENT FACTOR FOR AMBIENT LIGHTING CALIBRATION - A method, system, and apparatus that can be used to operate a display device in an energy efficient manner. The energy efficient display device can effectively and efficiently compensate for changes in ambient light incident at a display screen of the display device using an internal ambient light sensor to provide control signals to a backlight driver. Data from the ambient light sensor can be at least partially corrected to correspond more closely to a response of a Lambertian responsive light sensor | 01-26-2012 |
| 20120026202 | INTERRUPT-BASED NOTIFICATIONS FOR DISPLAY SETTING CHANGES - The disclosed embodiments relate to a system that communicates a change in a display setting from a display to a host system for the display. During operation, the system determines at the display that the display setting has changed. Next, in response to the change, the system sends an interrupt from the display to the host system through a first interface, wherein the interrupt informs the host system that the display setting has changed. After sending the interrupt to the host system, the system receives a request from the host system to obtain values for one or more display settings including the changed display setting. In response to the request, the system sends updated values for the one or more display settings to the host system. | 02-02-2012 |
| 20120281008 | COLOR CORRECTION METHOD AND APPARATUS FOR DISPLAYS - Method and apparatus for adjusting the display characteristics of an electronic display, such as a computer or television display. The display is color corrected, e.g., at the factory, to measure its white point correction, gamma and gray tracking correction, and the gain correction over time as the display warms up. Moreover the white point correction and the gamma correction are performed on a per unit basis for each individual display to be manufactured. The resulting correction parameters are stored in memory or firmware associated with the display. Thereby when the display is in use, it performs compensation for white point, gray tracking and gain correction as the display warms up, each time it is powered up or when its thermal operation conditions change. | 11-08-2012 |
| 20120313911 | AMBIENT LIGHT CALIBRATION FOR ENERGY EFFICIENCY IN DISPLAY SYSTEMS - A method, system, and apparatus that can be used to operate a display device in an energy efficient manner. The energy efficient display device can effectively and efficiently compensate for changes in ambient light incident at a display screen of the display device using an internal ambient light sensor to provide control signals to a backlight driver. | 12-13-2012 |
| 20140198093 | LOW POWER DISPLAY DEVICE WITH VARIABLE REFRESH RATES - The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below. | 07-17-2014 |
| 20140198114 | LOW POWER DISPLAY DEVICE WITH VARIABLE REFRESH RATES - The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below. | 07-17-2014 |
| 20140198138 | LOW POWER DISPLAY DEVICE WITH VARIABLE REFRESH RATES - The disclosure describes procedures for dynamically employing a variable refresh rate at an LCD display of a consumer electronic device, such as a laptop computer, a tablet computer, a mobile phone, or a music player device. In some configurations, the consumer electronic device can include a host system portion, having one or more processors and a display system portion, having a timing controller, a buffer circuit, a display driver, and a display panel. The display system can receive image data and image control data from a GPU of the host system, evaluate the received image control data to determine a reduced refresh rate (RRR) for employing at the display panel, and then transition to the RRR, whenever practicable, to conserve power. In some scenarios, the transition to the RRR can be a transition from a LRR of 50 hertz or above to a RRR of 40 hertz or below. | 07-17-2014 |
| 20150199292 | METHOD AND APPARATUS FOR SIMPLIFYING COMMUNICATION BETWEEN A HOST SYSTEM AND A DISPLAY SUBSYSTEM - A method for simplifying the host-to-display subsystem communications and consolidating the non-volatile memory requirements into a PMIC (power management integrated circuit) is disclosed. Hardware and software resource reduction in both the client devices (located in the display subsystem) and the host System on a Chip (SOC) can be realized with a novel PMIC design. The novel PMIC design achieves the resource reduction by providing for the following features: (1) Single-point communication, (2) Single-point notification, (3) Client device status storage, (4) Client device initialization from PMIC non-volatile memory, and (5) Subsystem calibration retrieval from PMIC non-volatile memory. | 07-16-2015 |
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| 20140184601 | SYSTEM AND METHOD FOR FRAME BUFFER DECOMPRESSION AND/OR COMPRESSION - A system and method for decompressing compressed data (e.g., in a frame buffer) and optionally recompressing the data. The method includes determining a portion of an image to be accessed from a memory and sending a conditional read corresponding to the portion of the image. In response to the conditional read, an indicator operable to indicate that the portion of the image is uncompressed may be received. If the portion of the image is compressed, in response to the conditional read, compressed data corresponding to the portion of the image is received. In response to receiving the compressed data, the compressed data is uncompressed into uncompressed data. The uncompressed data may then be written to the memory corresponding to the portion of the image. The uncompressed data may then be in-place compressed for or during subsequent processing. | 07-03-2014 |
| 20140184627 | PROGRESSIVE LOSSY MEMORY COMPRESSION - A method, in one embodiment, can include performing difference transformation of image samples. In addition, the method can also include performing length selection. The method can also include performing a prioritized ordering of difference data. Furthermore, the method can include performing packing that includes utilizing varying sized bit fields to produce a lossy compressed representation. | 07-03-2014 |
| 20140237187 | ADAPTIVE MULTILEVEL BINNING TO IMPROVE HIERARCHICAL CACHING - A device driver calculates a tile size for a plurality of cache memories in a cache hierarchy. The device driver calculates a storage capacity of a first cache memory. The device driver calculates a first tile size based on the storage capacity of the first cache memory and one or more additional characteristics. The device driver calculates a storage capacity of a second cache memory. The device driver calculates a second tile size based on the storage capacity of the second cache memory and one or more additional characteristics, where the second tile size is different than the first tile size. The device driver transmits the second tile size to a second coalescing binning unit. One advantage of the disclosed techniques is that data locality and cache memory hit rates are improved where tile size is optimized for each cache level in the cache hierarchy. | 08-21-2014 |
| 20140253555 | MULTIRESOLUTION CONSISTENT RASTERIZATION - A technique for multiresolution consistent rasterization in which a setup unit calculates universal edge equations for a universal resolution. A rasterizer evaluates coverage data for two different resolutions based on the edge equations. The rasterizer evaluates coverage data for different effective pixel sizes—a large pixel size and a small pixel size. Optionally, the rasterizer may determine a first set of coverage data by performing conservative rasterization to determine coverage data for large pixels. Optionally, the rasterizer may then determine a second set of coverage data by performing standard rasterization for small pixels. Optionally, for the second set of coverage data, the rasterizer may evaluate only the small pixels that are within large pixels in the first set of coverage data that evaluate as covered. | 09-11-2014 |
| 20140267224 | HANDLING POST-Z COVERAGE DATA IN RASTER OPERATIONS - Techniques are disclosed for storing post-z coverage data in a render target. A color raster operations (CROP) unit receives a coverage mask associated with a portion of a graphics primitive, where the graphics primitive intersects a pixel that includes a multiple samples, and the portion covers at least one sample. The CROP unit stores the coverage mask in a data field in the render target at a location associated with the pixel. One advantage of the disclosed techniques is that the GPU computes color and other pixel information only for visible fragments as determined by post-z coverage data. The GPU does not compute color and other pixel information for obscured fragments, thereby reducing overall power consumption and improving overall render performance. | 09-18-2014 |
| 20140267264 | GENERATING ANTI-ALIASED VOXEL DATA - One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves identifying a voxel that is intersected by a first graphics primitive that has a front side and a back side and selecting a plurality of sample points within the voxel. The technique further involves determining, for each sample point included in the plurality of sample points, whether the sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive. Finally, the technique involves storing, for at least a first sample point included in the plurality of sample points, a first result in a voxel mask reflecting whether the first sample point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive. | 09-18-2014 |
| 20140267265 | GENERATING ANTI-ALIASED VOXEL DATA - One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a first graphics primitive intersects a voxel and calculating a first set of coefficients associated with a first plane defined by the intersection of the first graphics primitive and the voxel. The technique further involves determining that a second graphics primitive intersects the voxel and calculating a second set of coefficients associated with a second plane defined by the intersection of the second graphics primitive and the voxel. The technique further involves calculating a third set of coefficients associated with a third surface based on the first set of coefficients and the second set of coefficients. The technique further involves calculating at least one of an amount of the voxel that is located on the back side of the third surface and an occlusion value based on the third set of coefficients. | 09-18-2014 |
| 20140267266 | GENERATING ANTI-ALIASED VOXEL DATA - One embodiment of the present invention sets forth a technique for performing voxelization. The technique involves determining that a voxel is intersected by a first graphics primitive that has a front side and a back side and selecting one or more reference points within the voxel. The technique further involves, for each reference point, determining a distance from the reference point to the first graphics primitive and storing a first scalar value in an array based on the distance. The sign of the first scalar value reflects whether the reference point is located on the front side of the first graphics primitive or on the back side of the first graphics primitive. | 09-18-2014 |
| 20140267318 | PIXEL SHADER BYPASS FOR LOW POWER GRAPHICS RENDERING - A computer-implemented method for drawing graphical objects within a graphics processing pipeline is disclosed. The method includes determining that a bypass mode for a first primitive is a no-bypass mode. The method further includes rasterizing the first primitive to generate a first set of rasterization results. The method further includes generating a first set of colors for the first set of rasterization results via a pixel shader unit. The method further includes rasterizing a second primitive to generate a second set of rasterization results. The method further includes generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any processing operations on the second set of rasterization results. The method further includes transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further processing. | 09-18-2014 |
| 20140267366 | TARGET INDEPENDENT RASTERIZATION WITH MULTIPLE COLOR SAMPLES - A graphics processing pipeline within a parallel processing unit (PPU) is configured to perform path rendering by generating a collection of graphics primitives that represent each path to be rendered. The graphics processing pipeline determines the coverage of each primitive at a number of stencil sample locations within each different pixel. Then, the graphics processing pipeline reduces the number of stencil samples down to a smaller number of color samples, for each pixel. The graphics processing pipeline is configured to modulate a given color sample associated with a given pixel based on the color values of any graphics primitives that cover the stencil samples from which the color sample was reduced. The final color of the pixel is determined by downsampling the color samples associated with the pixel. | 09-18-2014 |
| 20140267382 | EFFICIENT ROUND POINT RASTERIZATION - One embodiment of the present invention sets forth a technique for improved rasterization of round points mapped into a tile space within a graphics processing pipeline. A set of candidate tiles are selected based on proximity to a round point. A tile within the set of candidate tiles may be rejected based on a rejection boundary. A tile may be rejected if no vertex associated with the tile is within the coverage area. Performance is improved by rejecting certain unneeded tiles that would otherwise be included in conventional rasterization. One embodiment advantageously enlists line drawing circuitry to determine whether a given tile intersects the coverage area. | 09-18-2014 |
| 20140354634 | UPDATING DEPTH RELATED GRAPHICS DATA - Updating depth related graphics data is described. Geometric primitives are processed. Pixels are generated from the primitives based on the processing, each of which has at least one corresponding depth value. Culling is performed on a first group of the pixels, based on a representation of the at least one depth related value corresponding to each. Pixels may be discarded based on the culling and upon which a second group of pixels remain. A depth related raster operations function is performed, in which data is transacted with a depth buffer. The culling function is updated in relation to the transacting. The updating is performed on the basis of a granularity, which characterizes the culling function. | 12-04-2014 |
| 20150015594 | TECHNIQUES FOR OPTIMIZING STENCIL BUFFERS - One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment. | 01-15-2015 |
| 20150015595 | TECHNIQUES FOR OPTIMIZING STENCIL BUFFERS - One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment. | 01-15-2015 |
| 20150022519 | PIXEL SERIALIZATION TO IMPROVE CONSERVATIVE DEPTH ESTIMATION - One embodiment includes determining a first z-range for a first portion of a coarse raster tile, where the first portion includes a plurality of pixels having a first set of pixel locations, retrieving from a memory a corresponding z-range related to a second set of pixel locations associated with the coarse raster tile, where the first set of pixel locations comprises a subset of the second set of pixel locations, and comparing the first z-range to the corresponding z-range to determine whether the plurality of pixels is occluded. If the plurality of pixels determined to be occluded, then the plurality of pixels is culled. If the plurality of pixels is determined to not be occluded, then the plurality of pixels is transmitted to a fine raster unit for further processing. The coarse raster tile comprises a plurality of portions, including the first portion, and those portions are processed serially. | 01-22-2015 |
| 20150022537 | VARIABLE FRAGMENT SHADING WITH SURFACE RECASTING - A system, method, and computer program product are provided for shading primitive fragments. A target buffer may be recast when shaded samples that are covered by a primitive fragment are generated at a first shading rate using a first sampling mode, the shaded samples are stored in the target buffer that is associated with the first sampling mode and the first shading rate, a second sampling mode is determined, and the target buffer is associated with the second sampling mode. A sampling mode and/or shading rate may be changed for a primitive. A primitive fragment that is associated with a first sampling mode and a first shading rate is received and a second sampling mode is determined for the primitive fragment. Shaded samples corresponding to the primitive fragment are generated, at a second shading rate, using the second sampling mode and the shaded samples are stored in a target buffer. | 01-22-2015 |
| 20150049104 | RENDERING TO MULTI-RESOLUTION HIERARCHIES - One embodiment of the present invention includes techniques for processing a multi-resolution hierarchy, where an application configures a ROP unit to render all the levels included in the multi-resolution hierarchy to a single composite render target. The ROP unit renders memory pages to the composite render target in pitch order. In contrast, the texture unit accesses the composite render target with memory pages in pitch order for each level of the hierarchy. The application configures the MMU to ensure that the composite render target is correctly interpreted by the texture unit. Notably, the MMU translates ROP unit virtual addresses and texture unit virtual addresses using different mapping strategies to the same physical address space. One advantage of the disclosed embodiments is that rendering to the multi-resolution hierarchy does not require the CPU to execute the state parameter changes that are associated with rendering the different hierarchical levels using prior-art techniques. | 02-19-2015 |
| 20150049110 | RENDERING USING MULTIPLE RENDER TARGET SAMPLE MASKS - One embodiment sets forth a method for transforming 3-D images into 2-D rendered images using render target sample masks. A software application creates multiple render targets associated with a surface. For each render target, the software application also creates an associated render target sample mask configured to select one or more samples included in each pixel. Within the graphics pipeline, a pixel shader processes each pixel individually and outputs multiple render target-specific color values. For each render target, a ROP unit uses the associated render target sample mask to select covered samples included in the pixel. Subsequently, the ROP unit uses the render target-specific color value to update the selected samples in the render target, thereby achieving sample-level color granularity. Advantageously, by increasing the effective resolution using render target sample masks, the quality of the rendered image is improved without incurring the performance degradation associated with processing each sample individually. | 02-19-2015 |
| 20150070380 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR USING COMPRESSION WITH PROGRAMMABLE SAMPLE LOCATIONS - A system, method, and computer program product are provided for using compression with programmable sample locations, where the compression is a function of the programmable sample locations. The method includes the steps of storing a first value specifying a programmed sample location within a pixel in a sample pattern table and storing, in a memory, geometric surface parameters corresponding to a first attribute at the programmed sample location within a first pixel of a display surface. An instruction to store a second value specifying the programmed sample location within the pixel in the sample pattern table is received. The attribute is reconstructed based on the geometric surface parameters and the first value. | 03-12-2015 |
| 20150070381 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR USING COMPRESSION WITH PROGRAMMABLE SAMPLE LOCATIONS - A system, method, and computer program product are provided for using compression with programmable sample locations, where the compression is a function of the programmable sample locations. The method includes the steps of storing a first value specifying a programmed sample location within a pixel in a first sample pattern table that is associated with a first display surface and storing, in a memory, geometric surface parameters corresponding to a first attribute at the programmed sample location within a first pixel of the first display surface. A second value specifying the programmed sample location within the pixel in a second sample pattern table that is associated with a second display surface is also stored and the first attribute is reconstructed based on the geometric surface parameters and the first value. | 03-12-2015 |
| 20150084974 | TECHNIQUES FOR INTERLEAVING SURFACES - One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques. | 03-26-2015 |
| 20150138228 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING ANTI-ALIASING OPERATIONS USING A PROGRAMMABLE SAMPLE PATTERN TABLE - A system, method, and computer program product are provided for implementing anti-aliasing operations using a programmable sample pattern table. The method includes the steps of receiving an instruction that causes one or more values to be stored in one or more corresponding entries of the programmable sample pattern table and performing an anti-aliasing operation based on at least one value stored in the programmable sample pattern table. At least one value is selected from the programmable sample pattern table based on, at least in part, a location of one or more corresponding pixels. | 05-21-2015 |
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| 20140218390 | MODULATED AND BLENDED ANTI-ALIASING - A system, method, and computer program product are provided for anti-aliasing. During a first processing pass of a plurality of graphics primitives, z data is computed for multiple samples of each pixel in an image to generate a multi-sample z buffer. During a second processing pass of the graphics primitives, computed color values corresponding to each pixel in a color buffer that stores one color value for each pixel are accumulated. | 08-07-2014 |
| 20140267232 | CONSISTENT VERTEX SNAPPING FOR VARIABLE RESOLUTION RENDERING - A system, method, and computer program product are provided for adjusting vertex positions. One or more viewport dimensions are received and a snap spacing is determined based on the one or more viewport dimensions. The vertex positions are adjusted to a grid according to the snap spacing. The precision of the vertex adjustment may increase as at least one dimension of the viewport decreases. The precision of the vertex adjustment may decrease as at least one dimension of the viewport increases. | 09-18-2014 |
| 20140267238 | CONSERVATIVE RASTERIZATION OF PRIMITIVES USING AN ERROR TERM - A system, method, and computer program product are provided for conservative rasterization of primitives using an error term. In use, an edge equation is determined for each edge of a primitive, the edge equation having coefficients defining the edge of the primitive. Each edge of the primitive is shifted to enlarge the primitive by modifying coefficients of the edge equation defining the edge by an error term that is a predetermined amount. Pixels that intersect the primitive are then determined using the enlarged primitive. | 09-18-2014 |
| 20140267260 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR EXECUTING PROCESSES INVOLVING AT LEAST ONE PRIMITIVE IN A GRAPHICS PROCESSOR, UTILIZING A DATA STRUCTURE - A system, method, and computer program product are provided for executing processes involving at least one primitive in a graphics processor, utilizing a data structure. In operation, a data structure is associated with at least one primitive. Additionally, a plurality of processes involving the at least one primitive are executed in a graphics processor, utilizing the data structure. Moreover, the plurality of processes include at least one of selecting at least one surface or portion thereof to which to render, or selecting at least one of a plurality of viewports. | 09-18-2014 |
| 20140267315 | MULTI-SAMPLE SURFACE PROCESSING USING ONE SAMPLE - A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and an encoding state associated with the multi-sample pixel data is determined. Data for one sample of a multi-sample pixel and the encoding state are provided to a processing unit. The one sample of the multi-sample pixel is processed by the processing unit to generate processed data for the one sample that represents processed multi-sample pixel data for all samples of the multi-sample pixel or two or more samples of the multi-sample pixel. | 09-18-2014 |
| 20140267356 | MULTI-SAMPLE SURFACE PROCESSING USING SAMPLE SUBSETS - A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and is analyzed to identify subsets of samples of a multi-sample pixel that have equal data, such that data for one sample in a subset represents multi-sample pixel data for all samples in the subset. An encoding state is generated that indicates which samples of the multi-sample pixel are included in each one of the subsets. | 09-18-2014 |
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| 20090007972 | Water circulation system valve assemblies having water temperature control - A valve assembly for a water circulation system includes a valve body defining a bypass passage between a hot water side and a cold water side of the valve body. The bypass passage has a valve seat therein. A bypass valve is received within the bypass passage. The bypass valve restricts the flow of water through the bypass passage based on a temperature of the water in the bypass passage. The bypass valve is variably positionable with respect to the valve seat to control a bypass shut-off temperature of the water. | 01-08-2009 |
| 20090007975 | WATER CONTROL FIXTURE HAVING AUXILIARY FUNCTIONS - A water control fixture includes a housing having a plurality of ports defining a hot water inlet port, a cold water port, a fixture outlet port, and an auxiliary port, wherein water is dispensed from the housing via the fixture outlet port. A flow control unit is configured to be selectively positioned in fluid communication with different combinations of the plurality of ports, wherein the flow control unit has a main passage in fluid communication with the hot water inlet port, the cold water port, and the fixture outlet port. The flow control unit controls the flow of water from the hot water inlet port and the cold water port to the fixture outlet port. The flow control unit has an auxiliary passage in fluid communication with the auxiliary port and at least one of the hot water inlet port, the cold water port, and the fixture outlet port to perform an auxiliary function. | 01-08-2009 |
| 20090230200 | WATER CONTROL VALVE ASSEMBLY - A water control valve assembly includes a valve manifold having a mixing chamber for mixing water from a supply of hot water and a supply of cold water. The valve manifold has a water control element controlling the flow of water from the mixing chamber to a discharge port of the valve manifold. A thermostatically controlled bypass valve is in fluid communication with the valve manifold, wherein the bypass valve is configured to bypass water from the supply of hot water to the supply of cold water. | 09-17-2009 |
| 20100096025 | WATER CONTROL FIXTURE HAVING BYPASS VALVE - A faucet has a fixture body in fluid communication with a pressurized supply of hot water. The fixture body has a spout outlet configured to dispense water from the fixture body. At least one operating valve is coupled to the fixture body for controlling a flow of water to the spout outlet. A bypass valve is disposed in the fixture body for controlling a recirculating flow of water through the fixture body, where the bypass valve changes state when heated and when cooled to block and permit the recirculating flow of water based on a temperature of the water. | 04-22-2010 |
| 20100187816 | ELECTROLYSIS-RESISTANT COUPLING ASSEMBLY - An electrolysis-resistant coupling assembly for connection with a line fitting of a fluid line includes a fitting having a first mating surface and having an aperture extending therethrough, wherein the fitting is configured to be aligned with and face the line fitting for coupling thereto. The assembly also includes a coupler having one end provided with an outer coupler flange, the fitting being loaded onto the coupler such that the outer coupler flange passes through the aperture. The assembly also includes a substantially non-compressible, electrically non-conductive rigid captive ring. The captive ring is positioned against the outer coupler flange and interposed between the fitting and the coupler to provide electrical separation between the fitting and the coupler, wherein the fitting is held against the captive ring when the fitting is interconnected with the line fitting. | 07-29-2010 |
| 20100300555 | METHOD AND SYSTEM FOR CONTROLLED RELEASE OF HOT WATER FROM A FIXTURE - A valve assembly for a water circulation system includes a bypass valve with an inlet and an outlet that permits recirculating flow of water from a hot water line of the water circulation system. The valve assembly also includes a shut- off valve with a valve body having a hot water inlet and a hot water outlet configured to be coupled to a fixture of the water circulation system. The shut-off valve is located proximate the fixture and operating in an open position allowing water to flow to the hot water outlet and a closed position restricting water from flowing to the hot water outlet. The shut-off valve is configured to move automatically from the open position to the closed position in a controlled manner to limit discharge, from the hot water outlet, of water having a temperature below a desired level. | 12-02-2010 |
| 20110132989 | WATER CONTROL FIXTURE HAVING A FAILED CLOSED BYPASS VALVE - A water control fixture for use in a water circulation system includes a housing having a plurality of ports defining a hot water inlet port, a bypass port, and a fixture outlet port, wherein water is dispensed via the fixture outlet port. The water control fixture includes at least one operating valve disposed in the housing for controlling a flow of water from the hot water inlet port to the fixture outlet port, and a bypass valve disposed in the housing for controlling a flow of water through a bypass path between the hot water inlet port and the bypass port. The bypass valve includes a valve unit in the bypass path of the water circulation system that is operable in a closed state, an open state, and a failed state. The valve unit restricts water flow through the bypass path in the closed state, the valve unit allows water flow through the bypass path in the open state, and the valve unit restricts water flow through the bypass path in the failed state. The bypass valve includes a control mechanism in the bypass path of the water circulation system that is used for controlling the operation of the valve unit, wherein water flowing through the bypass path flows past the control mechanism. | 06-09-2011 |
| 20110259445 | WATER CIRCULATION SYSTEM VALVE ASSEMBLIES HAVING WATER TEMPERATURE CONTROL - A valve assembly for a water circulation system includes a valve body defining a bypass passage between a hot water side and a cold water side of the valve body. The bypass passage has a valve seat therein. A bypass valve is received within the bypass passage. The bypass valve restricts the flow of water through the bypass passage based on a temperature of the water in the bypass passage. The bypass valve is variably positionable with respect to the valve seat to control a bypass shut-off temperature of the water. | 10-27-2011 |
| 20120325918 | BYPASS VALVE FOR A WATER CIRCULATION SYSTEM - A bypass valve includes a housing having a hot water port configured to communicate with a hot water supply line and a return port configured to discharge water from the housing for recirculation to a hot water source. The housing has a passage permitting recirculating flow between the hot water port and the return port. A valve member is operable to allow and restrict recirculating flow through the passage. The valve member restricts water flow through the passage in a failed state. | 12-27-2012 |
| 20130180611 | WATER CONTROL FIXTURE HAVING AUXILIARY FUNCTIONS - A water control fixture includes a housing having a plurality of ports defining a hot water inlet port, a cold water port, a fixture outlet port, and an auxiliary port. A flow control unit is configured to be selectively positioned in fluid communication with different combinations of the plurality of ports, wherein the flow control unit has a main passage in fluid communication with the hot water inlet port, the cold water port, and the fixture outlet port. The flow control unit controls the flow of water from the hot water inlet port and the cold water port to the fixture outlet port. The flow control unit has an auxiliary passage in fluid communication with the auxiliary port and at least one of the hot water inlet port, the cold water port, and the fixture outlet port to perform an auxiliary function. | 07-18-2013 |
| 20130240053 | WATER CIRCULATION SYSTEM VALVE ASSEMBLIES HAVING WATER TEMPERATURE CONTROL - A valve assembly for a water circulation system includes a valve body defining a bypass passage between a hot water side and a cold water side of the valve body. The bypass passage has a valve seat therein. A bypass valve is received within the bypass passage. The bypass valve restricts the flow of water through the bypass passage based on a temperature of the water in the bypass passage. The bypass valve is variably positionable with respect to the valve seat to control a bypass shut-off temperature of the water. | 09-19-2013 |
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| 20090152218 | Dish rack with water drainage mechanism - A dish rack has a rack portion having a tray, the tray having an opening. The dish rack also includes a ramp provided. below the tray and positioned to receive water that flows through the opening of the tray. The ramp has a front end, a rear end, and a water outlet provided at the front end, the ramp being angled so that water flows from the rear end to the front end and then through the water outlet. | 06-18-2009 |
| 20090194532 | Trash Can With Power Operated Lid - A trash can include a sensor for detecting the presence of an object near a portion of the trash can. The detection of the object can be used to signal the trash can to open its lid. The trash can include an electronic drive unit for opening and closing the lid. | 08-06-2009 |
| 20110271438 | Shelving System - A shelving system can include can include an elongated support member and a plurality of shelves, each of which can be supported by a clamping mechanism. The support member can have a telescoping configuration so that upper and lower ends of the support member can be pressed against upper and lower stationary objects. | 11-10-2011 |
| 20120022618 | High Powered Light Emitting Diode Photobiology Device - A high-powered light emitting diode (LED) photobiology (phototherapy) device is disclosed in the accompanying specification. The contemplated photobiology (phototherapy) device may be used in the treatment of various aesthetic and medical or other conditions. The phototherapy device may include a number of select LEDs for emitting a desired range or ranges of wavelengths of high intensity light for use in treatment. Additionally, the phototherapy treatment includes one or more methods for providing a treatment appropriate to the condition desired to be treated. The phototherapy device provides for a variety of high power light settings, intensity levels, and selectable time intervals for providing treatment. | 01-26-2012 |
| 20130191987 | SHELVING SYSTEM - A shelving system can include can include an elongated support member and a plurality of shelves, each of which can be supported by a clamping mechanism. The support member can have a telescoping configuration so that upper and lower ends of the support member can be pressed against upper and lower stationary objects. | 08-01-2013 |
| 20150251849 | RECEPTACLE WITH BAG LINER DISPENSER - A receptacle assembly including a body portion having a front wall, a rear wall, and lateral sidewalls. The receptacle assembly can also include a bag liner dispenser disposed on an exterior surface of the rear wall, such that an interior surface of the rear wall remains generally planar. The bag liner dispenser can extend around a periphery of an opening that can provide access from the bag liner dispenser to an interior space of the body portion. | 09-10-2015 |
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| 20100248799 | ELECTRONIC DEVICE WITH SHARED MULTIBAND ANTENNA AND ANTENNA DIVERSITY CIRCUITRY - Electronic devices are provided that contain wireless communications circuitry. The wireless communications circuitry may have antenna diversity circuitry that allows an optimum antenna in an antenna structure to be switched into use during device operations. The antenna structure may be shared between multiple radio-frequency transceivers in a radio-frequency transceiver circuit. The radio-frequency transceiver circuit may be coupled to the antenna structure using switching and filtering circuitry. The filtering circuitry may include a diplexer that divides radio-frequency signals into a divided signal path based on frequency. The filtering circuitry may also include bandpass filters that are interposed in each branch of the divided signal path. Switching circuitry in the switching and filtering circuitry may be used to selectively configure the wireless communications circuitry in transmit and receive modes using multiple communications bands. | 09-30-2010 |
| 20100260082 | SHARED MULTIBAND ANTENNAS AND ANTENNA DIVERSITY CIRCUITRY FOR ELECTRONIC DEVICES - Electronic devices are provided that contain wireless communications circuitry. The wireless communications circuitry may have antenna diversity circuitry that allows an optimum antenna or optimum antennas in an antenna structure to be switched into use during device operations. The antenna structure may be shared between multiple radio-frequency transceivers in a radio-frequency transceiver circuit. The radio-frequency transceiver circuit may be coupled to the antenna structure using switching and filtering circuitry. The filtering circuitry may include one or more diplexers that divide radio-frequency signals into divided signal paths based on frequency. The filtering circuitry may also include low pass, high pass, and bandpass filters that are interposed in the divided signal paths. Switching circuitry in the switching and filtering circuitry may be used to selectively configure the wireless communications circuitry in transmit and receive modes using multiple communications bands. | 10-14-2010 |
| 20110136493 | METHODS FOR GEOGRAPHIC OPTIMIZATION OF CELLULAR TELEPHONE TRANSMIT POWER SETTINGS - Portable user devices are provided that communicate wirelessly with base stations. A user device may include a transceiver, a power amplifier, a voltage supply, and a global positioning system (GPS) unit. The device may transmit signals at a certain transmit power to a neighboring base station. The device may log the time spent transmitting at each power level. Each data point may be tagged with the current location of the device. The logs of each device may be aggregated by a power optimization server. The power optimization server may calculate optimum power settings for each region and for each type of device. A region may be any desirable size ranging from the size of a single cell to an entire continent. Device users may download updated optimum settings. A device may automatically detect and select the optimum transmit power setting during operation depending on its current location. | 06-09-2011 |
| 20110319035 | WIRELESS CIRCUITS WITH MINIMIZED PORT COUNTS - An electronic device has wireless communications circuitry including a triplexer. The wireless communications circuitry may be used in first and second modes. In the first mode, the device communicates in a first communications band using a transmitter in a first uplink frequency range associated with the first communications band and using a receiver in a first downlink frequency range associated with the first communications band. In the second mode, the device communicates in a second communications band using a transmitter to transmit in a second uplink frequency range associated with the second communications band and using the receiver to receive in a second downlink frequency range associated with the second communications band. Signals in the two downlink frequency ranges may pass through a common bandpass filter in the triplexer. Two additional bandpass filters in the triplexer may be used to respectively handle the two uplink frequency ranges. | 12-29-2011 |
| 20120009887 | WIRELESS CIRCUITRY WITH REDUCED HARMONIC INTERFERENCE - An electronic device has wireless communications circuitry that includes transmitters and receivers. Antenna structures may be coupled to the transmitters and receivers to support radio-frequency signal transmission and radio-frequency signal reception operations. Switching circuitry such as first and second radio-frequency switches may be used to support multiple communications bands of interest. A low band set of transmitters may be associated with the first switch and a high band set of transmitters may be associated with the second switch. The switches can be configured in real time to switch a desired communications band into use. As transmitted signals at frequency f pass through the switches, harmonics at | 01-12-2012 |
| 20130016633 | Wireless Circuitry for Simultaneously Receiving Radio-frequency Transmissions in Different Frequency BandsAANM Lum; Nicholas W.AACI Santa ClaraAAST CAAACO USAAGP Lum; Nicholas W. Santa Clara CA USAANM Dimpflmaier; Ronald W.AACI Los GatosAAST CAAACO USAAGP Dimpflmaier; Ronald W. Los Gatos CA USAANM Sanguinetti; Louie J.AACI Los GatosAAST CAAACO USAAGP Sanguinetti; Louie J. Los Gatos CA US - An electronic device has wireless communications circuitry that includes transmitters and receivers. Antenna structures may be coupled to the transmitters and receivers to support radio-frequency signal transmission and radio-frequency signal reception operations. Switching circuitry such may be used to support multiple communications bands of interest. One or more low band receivers may be associated with the first switch and one or more high band receivers may be associated with the second switch. The switches can be configured in real time to switch a desired communications band into use. A diplexer may be used to simultaneously pass low bands to the first receiver and high bands to the second receiver. In this way, a data stream in the low band may be simultaneously received with a data stream in the high band. | 01-17-2013 |
| 20130045700 | WIRELESS ELECTRONIC DEVICE WITH ANTENNA CYCLING - A wireless electronic device may contain multiple antennas. Control circuitry in the wireless electronic device may adjust antenna switching circuitry so that the device repeatedly cycles through use of each of the antennas. In a device with first and second antennas, the device may repeatedly toggle between the first and second antennas. During each toggling cycle time period, the first antenna may transmit for a fraction of the time period and the second antenna may transmit for a fraction of the time period. The wireless device may control the average power emitted by each antenna by adjusting the fractions of time assigned to each antenna. By performing antenna toggling, the average transmit power produced by each antenna may be reduced while maintaining the average transmit power produced by the device at a desired level. | 02-21-2013 |
| 20130045744 | METHOD FOR OPTIMIZING POWER CONSUMPTION IN WIRELESS DEVICES USING DATA RATE EFFICIENCY FACTOR - An electronic device has wireless communications circuitry that supports communications using multiple radio access technologies. The electronic device may gather information such as data rate values, power consumption values, and other data for a currently active radio access technology and an alternative radio access technology. The electronic device may automatically switch between the currently active radio access technology and the alternative radio access technology based on a value of a data rate efficiency metric. The data rate efficiency metric may represent how efficiently each radio access technology is capable of using power to convey a given amount of data per unit time. The data rate efficiency metric may be evaluated using measured power consumption data, measured data rate values, and operating parameters such as signal strength and transmitted power parameters. | 02-21-2013 |
| 20130059546 | Radio-Frequency Power Amplifier Circuitry with Power Supply Voltage Optimization Capabilities - Electronic devices with wireless communications capabilities are provided. The electronic device may include storage and processing circuitry, power amplifier circuitry, power supply circuitry, etc. The storage and processing circuitry may direct the power amplifier circuitry to operate using a desired power mode, in allocated resource blocks within a particular frequency channel, and at a given output power level. The power supply circuitry may bias the power amplifier circuitry with a power supply voltage. The electronic device may be subject to in-band emissions requirements and adjacent channel leakage requirements that restrict the power levels produced by the device on frequencies that are not allocated to the device. The electronic device may optimize the power amplifier supply voltage based on allocated resource blocks by minimizing the supply voltage to reduce power consumption while ensuring that emissions requirements are satisfied. | 03-07-2013 |
| 20130065541 | Radio-Frequency Power Amplifier Circuitry with Linearity Optimization Capabilities - An electronic device may be located in a geographical cell that is served by a base station. The electronic device may communicate with the base station on a frequency band. The frequency band may be subject to adjacent band emissions requirements to help prevent interference with wireless devices that are operating in adjacent frequency bands. The adjacent band emission requirements may vary based on the frequency band used to communicate with the base station, the geographical cell, and/or the presence of public safety radios. To satisfy the adjacent band emissions requirements while minimizing power consumption, the electronic device may receive cell information from the base station and adjust power amplifier linearity based on the received information. | 03-14-2013 |
| 20130148636 | Wireless electronic device with antenna switching circuitry - A wireless electronic device may include antennas formed at different locations on the device. The wireless electronic device may include transceivers that are used to wirelessly communicate in different frequency bands by transmitting and receiving radio-frequency signals in the frequency bands. The transceivers may include Wi-Fi® transceivers and cellular transceivers such as Long Term Evolution transceivers. The wireless electronic device may include antenna switching circuitry interposed between the transceivers and the antennas. The wireless electronic device may include control circuitry that controls the antenna switching circuitry to ensure that radio-frequency transmissions in adjacent frequency bands are routed to different antennas. By routing radio-frequency transmissions in adjacent frequency bands to different antennas, self-interference between communications in the adjacent frequency bands may be reduced. Self-interference may also be reduced by performing time division multiplexing to isolate radio-frequency signals that are transmitted in adjacent frequency bands. | 06-13-2013 |
| 20130190038 | Electronic Device With Dynamic Amplifier Linearity Control - An electronic device may include antenna structures. Wireless transmitter circuitry such as cellular telephone transmitter circuitry and wireless local area network circuitry may transmit signals using the antenna structures. A wireless receiver may receive signals from the antenna structures through an adjustable-linearity amplifier. The wireless receiver may operate in a receive band such as a satellite navigation system receive band. During operation of the electronic device, control circuitry in the device may analyze the frequencies and powers of the transmitted signals to determine whether there is a potential for interference for the receive band to be generated in the adjustable-linearity amplifier. In response to determining that there is a potential for interference, the control circuitry may increase the linearity of the adjustable-linearity amplifier. | 07-25-2013 |
| 20140160955 | Method for Validating Radio-Frequency Self-Interference of Wireless Electronic Devices - A test system for testing a wireless electronic device is provided. The test system may include a test host and a tester. The test host may instruct a wireless electronic device under test (DUT) to transmit radio-frequency uplink signals in selected uplink resource blocks of an uplink channel in a desired Long Term Evolution (LTE) frequency band. The tester may convey radio-frequency test data to the DUT in a selected downlink resource block of a downlink channel in the desired LTE frequency band. The DUT may measure data reception throughput values associated with the test data. The test host may compare the measured data reception throughput values to threshold data reception throughput values to characterize the radio-frequency performance of the DUT. The test system may test the radio-frequency performance of the DUT for test data in some or all downlink resource blocks of the downlink channel. | 06-12-2014 |
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| 20090083830 | Systems and Methods of Controlling Network Access - A new approach to network security includes manipulating an access point such that an initial communication from an external device is passed to a restricted subset of a computing network including a gatekeeper. The gatekeeper is configured to enforce a security policy against the external device before granting access to a less-restricted subset of the computing network. If requirements of the security policy are satisfied, then the gatekeeper reconfigures the access point such that further communication from the external device may be received by elements of the less-restricted subset. Enforcement of the security policy optionally includes performing a security audit of the external device. | 03-26-2009 |
| 20100005506 | DYNAMIC ADDRESS ASSIGNMENT FOR ACCESS CONTROL ON DHCP NETWORKS - Systems and methods of managing security on a computer network are disclosed. The computer network includes a restricted subnet and a less-restricted subnet. Access to the restricted subnet is controlled by a network filter, optionally inserted as a software shim on a DHCP server. In some embodiments, the network filter is configured to manipulate relay IP addresses to control whether the DHCP server provides, in a DHCPOFFER packet, an IP address that can be used to access the restricted subset. In some embodiments, configuration information is communicated between the DHCP server and the network filter via DHCPOFFER packets. | 01-07-2010 |
| 20110231915 | SYSTEMS AND METHODS OF CONTROLLING NETWORK ACCESS - A new approach to network security includes manipulating an access point such that an initial communication from an external device is passed to a restricted subset of a computing network including a gatekeeper. The gatekeeper is configured to enforce a security policy against the external device before granting access to a less-restricted subset of the computing network. If requirements of the security policy are satisfied, then the gatekeeper reconfigures the access point such that further communication from the external device may be received by elements of the less-restricted subset. Enforcement of the security policy optionally includes performing a security audit of the external device. | 09-22-2011 |
| 20110231916 | SYSTEMS AND METHODS OF CONTROLLING NETWORK ACCESS - A new approach to network security includes manipulating an access point such that an initial communication from an external device is passed to a restricted subset of a computing network including a gatekeeper. The gatekeeper is configured to enforce a security policy against the external device before granting access to a less-restricted subset of the computing network. If requirements of the security policy are satisfied, then the gatekeeper reconfigures the access point such that further communication from the external device may be received by elements of the less-restricted subset. Enforcement of the security policy optionally includes performing a security audit of the external device. | 09-22-2011 |
| 20110231928 | SYSTEMS AND METHODS OF CONTROLLING NETWORK ACCESS - A new approach to network security includes manipulating an access point such that an initial communication from an external device is passed to a restricted subset of a computing network including a gatekeeper. The gatekeeper is configured to enforce a security policy against the external device before granting access to a less-restricted subset of the computing network. If requirements of the security policy are satisfied, then the gatekeeper reconfigures the access point such that further communication from the external device may be received by elements of the less-restricted subset. Enforcement of the security policy optionally includes performing a security audit of the external device. | 09-22-2011 |
| 20120131637 | Systems and Methods of Controlling Network Access - A new approach to network security includes manipulating an access point such that an initial communication from an external device is passed to a restricted subset of a computing network including a gatekeeper. The gatekeeper is configured to enforce a security policy against the external device before granting access to a less-restricted subset of the computing network. If requirements of the security policy are satisfied, then the gatekeeper reconfigures the access point such that further communication from the external device may be received by elements of the less-restricted subset. Enforcement of the security policy optionally includes performing a security audit of the external device. | 05-24-2012 |
| 20120246698 | SYSTEMS AND METHODS OF CONTROLLING NETWORK ACCESS - A new approach to network security includes manipulating an access point such that an initial communication from an external device is passed to a restricted subset of a computing network including a gatekeeper. The gatekeeper is configured to enforce a security policy against the external device before granting access to a less-restricted subset of the computing network. If requirements of the security policy are satisfied, then the gatekeeper reconfigures the access point such that further communication from the external device may be received by elements of the less-restricted subset. Enforcement of the security policy optionally includes performing a security audit of the external device. | 09-27-2012 |
| 20120254937 | SYSTEMS AND METHODS OF CONTROLLING NETWORK ACCESS - A new approach to network security includes manipulating an access point such that an initial communication from an external device is passed to a restricted subset of a computing network including a gatekeeper. The gatekeeper is configured to enforce a security policy against the external device before granting access to a less-restricted subset of the computing network. If requirements of the security policy are satisfied, then the gatekeeper reconfigures the access point such that further communication from the external device may be received by elements of the less-restricted subset. Enforcement of the security policy optionally includes performing a security audit of the external device. | 10-04-2012 |
| 20120254938 | SYSTEMS AND METHODS OF CONTROLLING NETWORK ACCESS - A new approach to network security includes manipulating an access point such that an initial communication from an external device is passed to a restricted subset of a computing network including a gatekeeper. The gatekeeper is configured to enforce a security policy against the external device before granting access to a less-restricted subset of the computing network. If requirements of the security policy are satisfied, then the gatekeeper reconfigures the access point such that further communication from the external device may be received by elements of the less-restricted subset. Enforcement of the security policy optionally includes performing a security audit of the external device. | 10-04-2012 |
| 20120254939 | SYSTEMS AND METHODS OF CONTROLLING NETWORK ACCESS - A new approach to network security includes manipulating an access point such that an initial communication from an external device is passed to a restricted subset of a computing network including a gatekeeper. The gatekeeper is configured to enforce a security policy against the external device before granting access to a less-restricted subset of the computing network. If requirements of the security policy are satisfied, then the gatekeeper reconfigures the access point such that further communication from the external device may be received by elements of the less-restricted subset. Enforcement of the security policy optionally includes performing a security audit of the external device. | 10-04-2012 |
