Patent application number | Description | Published |
20080298130 | MEMORY DEVICE DISTRIBUTED CONTROLLER SYSTEM - A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command. | 12-04-2008 |
20100174855 | MEMORY DEVICE CONTROLLER - A controller for a memory device and methods are provided. The controller has an updateable register bank adapted to send a first signal to an analog/memory core of the memory device for controlling operation of the analog/memory core. The analog/memory core has an array of flash memory cells and supporting analog access circuitry. A bus controller is coupled to the register bank. The bus controller is adapted to receive a second signal from the register bank and to send a third signal to the register bank for updating the register bank. A select register is coupled to the register bank. A processor is coupled to the bus controller and the select register. | 07-08-2010 |
20100246265 | ERASE CYCLE COUNTER USAGE IN A MEMORY DEVICE - Memory devices and methods are disclosed to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example. | 09-30-2010 |
20120026792 | ERASE CYCLE COUNTER USAGE IN A MEMORY DEVICE - Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and is stored in the associated block of memory. Programming voltage levels utilized during program operations of memory cells are determined, at least in part, based upon the value of the erase cycle counter stored in a memory block undergoing a programming operation, for example. | 02-02-2012 |
20120131267 | MEMORY DEVICE DISTRIBUTED CONTROLLER SYSTEM - A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave controllers can include a data cache controller that is coupled to and controls the data cache and an analog controller that is coupled to and controls the analog voltage generation circuit. The respective controllers have appropriate software/firmware instructions that determine the response the respective controllers take in response to the received command. | 05-24-2012 |
20130227203 | DYNAMIC SLC/MLC BLOCKS ALLOCATIONS FOR NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 08-29-2013 |
20140032886 | MEMORY CONTROLLERS - Methods and controllers for executing an instruction set are provided. In one such method, executing an instruction set includes executing an instruction of one type in the instruction set, executing a context switch instruction, and executing an instruction of a second type in the instruction set. in one such controller, a single machine executes instructions in an instruction set with instructions having an operational code, and instructions that do not have an operational code. | 01-30-2014 |
20140133226 | ERASING PHYSICAL MEMORY BLOCKS OF NON-VOLATILE MEMORY - Apparatus and methods are disclosed, such as those that provide dynamic block allocations in NAND flash memory between single-level cells (SLC) and multi-level cells (MLC) based on characteristics. In one embodiment, a memory controller dynamically switches between programming and/or reprogramming blocks between SLC mode and MLC mode based on the amount of memory available for use. When memory usage is low, SLC mode is used. When memory usage is high, MLC mode is used. Dynamic block allocation allows a memory controller to obtain the performance and reliability benefits of SLC mode while retaining the space saving benefits of MLC mode. | 05-15-2014 |
20140156904 | BUS CONTROLLER - A bus controller has a displacer, an arithmetic logic unit coupled to the displacer, and a replacer selectively coupled to the displacer and the arithmetic logic unit. | 06-05-2014 |