Patent application number | Description | Published |
20080203468 | FinFET with Reduced Gate to Fin Overlay Sensitivity - Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure. | 08-28-2008 |
20080206978 | ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A structure fabrication method. The method includes providing a structure. The structure includes (a) a substrate layer, (b) a first fuse electrode in the substrate layer, and (c) a fuse dielectric layer on the substrate layer and the first fuse electrode. The method further includes (i) forming an opening in the fuse dielectric layer such that the first fuse electrode is exposed to a surrounding ambient through the opening, (ii) forming a fuse region on side walls and bottom walls of the opening such that the fuse region is electrically coupled to the first fuse electrode, and (iii) after said forming the fuse region, filling the opening with a dielectric material. | 08-28-2008 |
20080217614 | Systems and Methods for Controlling of Electro-Migration - Systems and methods for controlling electro-migration, and reducing the deleterious effects thereof, are disclosed. Embodiments provide for reversal of an applied voltage to an integrated circuit when a measurement indicative of an extent of electro-migration indicates that a healing cycle of operation is warranted. During the healing cycle, circuits of the integrated circuit function normally, but electro-migration effects are reversed. In one embodiment, micro-electro-mechanical switches are provided at a lowest level of metallization to switch the direction of current through the levels of metallization of the integrated circuit. In another embodiment, if the measurement indicative of the extent of electro-migration exceeds a reference level by a specifiable amount, then the voltage applied to the integrated circuit is reversed in polarity to cause current to switch directions to counter electro-migration. A plurality of switches are provided to switch current directions through a lowest level of metallization so that the circuits function normally even though the polarity of the applied voltage has been reversed. | 09-11-2008 |
20080218290 | Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry - An impedance matcher that automatically matches impedance between a driver and a receiver. The impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver. | 09-11-2008 |
20080220583 | SEMICONDUCTOR DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATING SUCH STRUCTURES - Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure comprises a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further comprises a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body. | 09-11-2008 |
20080224175 | SEMICONDUCTOR DEVICE STRUCTURES FOR BIPOLAR JUNCTION TRANSISTORS AND METHODS OF FABRICATING SUCH STRUCTURES - Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure includes a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further includes a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body. | 09-18-2008 |
20080227425 | APPARATUS FOR IMPLEMENTING ENHANCED HAND SHAKE PROTOCOL IN MICROELECTRONIC COMMUNICATION SYSTEMS - A method and apparatus are provided for implementing an enhanced hand shake protocol for microelectronic communication systems. A transmitter and a receiver is coupled together by a transmission link. The transmitter receives an idle input. The idle input is activated when the transmitter is not transmitting data and the transmitter applies a first common mode level to the receiving unit. The idle input is deactivated when the transmitter is ready to transmit data and the transmitter raises the common mode level to the receiving unit. Responsive to the receiver detecting the common mode level up-movement, then the receiver receives the transmitted data signals. After the desired data has been sent, the transmitter terminates communications, drops the common mode level with the idle input being activated. | 09-18-2008 |
20080258857 | ELECTRONIC FUSE WITH CONFORMAL FUSE ELEMENT FORMED OVER A FREESTANDING DIELECTRIC SPACER - An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element. | 10-23-2008 |
20080272412 | METHOD AND STRUCTURE TO REDUCE CONTACT RESISTANCE ON THIN SILICON-ON-INSULATOR DEVICE - A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device. | 11-06-2008 |
20080274597 | METHOD AND STRUCTURE TO REDUCE CONTACT RESISTANCE ON THIN SILICON-ON-INSULATOR DEVICE - A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device. | 11-06-2008 |
20080283920 | HYBRID ORIENTED SUBSTRATES AND CRYSTAL IMPRINTING METHODS FOR FORMING SUCH HYBRID ORIENTED SUBSTRATES - A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided. | 11-20-2008 |
20080286888 | TEST STRUCTURES AND METHODOLOGY FOR DETECTING HOT DEFECTS - Test structures for detecting defects arising from hybrid orientation technology (HOT) through detection of device leakage (gate leakage, junction leakage, and sub-threshold leakage), having at least one active region disposed in a re-grown region of a substrate: a layer of oxide; a layer of poly. Some test structures are dog-bone shaped test structure, tower shaped test structure, and inside-hole shaped. A method for detecting HOT defects involves measuring defect size and location in terms of device leakage, such as gate leakage, junction leakage, and sub-threshold leakage. HOT edge defect density and edge defect size distribution may be calculated, and the resulting defect information may be used to calibrate a defect yield model. | 11-20-2008 |
20080318360 | DEVICE AND METHOD FOR FABRICATING DOUBLE-SIDED SOI WAFER SCALE PACKAGE WITH OPTICAL THROUGH VIA CONNECTIONS - A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system. | 12-25-2008 |
20090001426 | Integrated Fin-Local Interconnect Structure - Embodiments of the invention generally relate to semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits. | 01-01-2009 |
20090001477 | Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures - Embodiments of the invention generally relate to semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers. | 01-01-2009 |
20090007036 | Integrated Fin-Local Interconnect Structure - Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits. | 01-01-2009 |
20090007037 | Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures - Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers. | 01-01-2009 |
20090073796 | MEMORY ARRAY PERIPHERAL STRUCTURES AND USE - A method for using photolithographic dummy memory cells arranged in rings around a set of primary memory cells as test structures and as redundant memory cells. Also circuits and structures of memory arrays having multiple-use dummy memory cells. | 03-19-2009 |
20090115448 | Design Structure for an Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry - A design structure for an impedance matcher that automatically matches impedance between a driver and a receiver. The design structure for an impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver. | 05-07-2009 |
20090121312 | METHOD AND APPARATUS FOR MAKING COPLANAR ISOLATED REGIONS OF DIFFERENT SEMICONDUCTOR MATERIALS ON A SUBSTRATE - A semiconductor processing method includes providing a substrate, forming a plurality of semiconductor layers in the substrate, each of the semiconductor layers being distinct and selected from different groups of semiconductor element types. The semiconductor layers include a first, second, and third semiconductor layers. The method further includes forming a plurality of lateral void gap isolation regions for isolating portions of each of the semiconductor layers from portions of the other semiconductor layers. | 05-14-2009 |
20100039191 | ACTIVE INDUCTOR FOR ASIC APPLICATION - An apparatus and method for manufacturing low-cost high-density compact active inductor module using existing DRAM, SRAM and logic process integration. The elements of the active inductor modules are formed by three semiconductor devices including nMOS devices, deep-trench capacitors and a polysilicon or TaN resistor. The active inductor modules can be connected in a parallel and/or serial configuration to obtain a wide range of inductance values. The modular active inductors can be advantageously stored in an ASIC library to facilitate a flexible and convenient circuit design. | 02-18-2010 |
20100176506 | THERMOELECTRIC 3D COOLING - The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips. | 07-15-2010 |
20100182040 | PROGRAMMABLE THROUGH SILICON VIA - Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack. | 07-22-2010 |
20100182041 | 3D CHIP-STACK WITH FUSE-TYPE THROUGH SILICON VIA - Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack. | 07-22-2010 |
20100261318 | 3D CHIP-STACK WITH FUSE-TYPE THROUGH SILICON VIA - Programmable fuse-type through silicon vias (TSVs) in silicon chips are provided with non-programmable TSVs in the same chip. The programmable fuse-type TSVs may employ a region within the TSV structure having sidewall spacers that restrict the cross-sectional conductive path of the TSV adjacent a chip surface contact pad. Application of sufficient current by programming circuitry causes electromigration of metal to create a void in the contact pad and, thus, an open circuit. Programming may be carried out by complementary circuitry on two adjacent chips in a multi-story chip stack. | 10-14-2010 |
20100277210 | THREE-DIMENSIONAL CHIP-STACK SYNCHRONIZATION - a central reference clock is placed in a substantially middle chip of a 3-D chip-stack. The central reference clock is distributed to each child chip of the 3-D chip-stack, so that a plurality of clocks is generated for each individual chip in the 3-D-stack in a synchronous manner. A predetermined number of through-silicon-vias and on-chip wires are employed to form a delay element for each slave clock, ensuring that the clock generated for each child chip is substantially synchronized. Optionally, an on-chip clock trimming circuit is embedded for further precision tuning to eliminate local clock skews. | 11-04-2010 |
20100301475 | Forming Semiconductor Chip Connections - Systems and methods are disclosed that enable forming semiconductor chip connections. In one embodiment, the semiconductor chip includes a body having a polyhedron shape with a pair of opposing sides; and a solder member extending along a side that extends between the pair of opposing sides of the polyhedron shape. | 12-02-2010 |
20100320563 | ELECTRONIC FUSES IN SEMICONDUCTOR INTEGRATED CIRCUITS - A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element. | 12-23-2010 |
20100327958 | Leakage Current Mitigation in a Semiconductor Device - A dormant mode target semiconductor device within a leakage current target unit is identified for mitigating leakage current to prevent it from reaching catastrophic runaway. A leakage current shift monitor unit is electrically connected to the output node of the leakage current target unit and collects leakage current from the selected target semiconductor device for two consecutive predefined temporal periods and measures the difference between the collected leakage currents. A comparator receives and compares the outputs of the current shift monitor unit and a reference voltage generator. The comparator propagates an alert signal to the leakage current target unit when the leakage voltage output from the leakage current shift monitor unit exceeds the reference voltage, a condition that indicates that the leakage current is about to approach catastrophic runaway levels. This alert signal switches the target semiconductor device to an active mode for leakage mitigation, which includes a repair voltage from a repair voltage generator applied to the gate of the target semiconductor device. | 12-30-2010 |
20110034021 | PROGRAMMABLE THROUGH SILICON VIA - Through silicon vias (TSVs) in silicon chips are both programmable and non-programmable. The programmable TSVs may employ metal/insulator/metal structures to switch from an open to shorted condition with programming carried out by complementary circuitry on two adjacent chips in a multi-story chip stack. | 02-10-2011 |
20110104846 | Thermoelectric 3D Cooling - The invention comprises a 3D chip stack with an intervening thermoelectric coupling (TEC) plate. Through silicon vias in the 3D chip stack transfer electronic signals among the chips in the 3D stack, power the TEC plate, as well as distribute heat in the stack from hotter chips to cooler chips. | 05-05-2011 |
20110175215 | 3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP - A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip. | 07-21-2011 |
20120126342 | FIELD EFFECT TRANSISTORS WITH LOW K SIDEWALL SPACERS AND METHODS OF FABRICATING SAME - Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation. | 05-24-2012 |
20120146112 | FINFET WITH REDUCED GATE TO FIN OVERLAY SENSITIVITY - Embodiments of the invention provide a relatively uniform width fin in a Fin Field Effect Transistors (FinFETs) and apparatus and methods for forming the same. A fin structure may be formed such that the surface of a sidewall portion of the fin structure is normal to a first crystallographic direction. Tapered regions at the end of the fin structure may be normal to a second crystal direction. A crystallographic dependent etch may be performed on the fin structure. The crystallographic dependent etch may remove material from portions of the fin normal to the second crystal direction relatively faster, thereby resulting in a relatively uniform width fin structure. | 06-14-2012 |
20120248567 | LAYERED STRUCTURE WITH FUSE - A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material. | 10-04-2012 |
20130193574 | 3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP - A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip. | 08-01-2013 |