Patent application number | Description | Published |
20090251976 | Method and apparatus for DQS postamble detection and drift compensation in a double data rate (DDR) physical interface - Circuitry for reading from a double data rate type memory, the circuitry including control logic, a first bi-directional input/output interface (I/O) configured to be coupled to a data bus of a double data rate type memory and to receive therefrom a data transmission having a duration selected by the control logic, a second bi-directional input/output interface (I/O) configured to be coupled to a data strobe line of the double data rate type memory, a gate coupled to the second bi-directional input/output interface configured for controlling the duration of a data strobe signal received along the data strobe line in response to a data strobe masking gating signal and a data strobe masking gating signal modifier applying to the expected data receipt duration indicating signal a variable time delay such as to center the expected data receipt duration indicating signal about the midpoint of the duration of the data transmission. | 10-08-2009 |
20130291130 | Protection of Memory Field Using Illegal Values - An electronic device ( | 10-31-2013 |
20130305372 | Preventing Unauthorized Data Extraction - An electronic device ( | 11-14-2013 |
20140009995 | Protection of Stored Data Using Optical Emitting Elements - An integrated circuit device ( | 01-09-2014 |
20140143883 | Preventing Data Extraction by Side-Channel Attack - A method for data transfer includes receiving a control signal triggering a transfer of a secret value into an element ( | 05-22-2014 |
20150072447 | DETECTION OF DISASSEMBLY OF MULTI-DIE CHIP ASSEMBLIES - A multi-die chip assembly is described, the multi-die chip assembly including at least one detection apparatus which detects manipulations of the multi-die chip assembly, the detection apparatus including a distributed circuit including a circuit whose elements are distributed among those dies which include the elements of a local reference circuit, the distributed circuit including a free running clock, at least one local reference circuit disposed in at least one die of the multi-die chip assembly, each of the local reference circuits including a free running clock, and at least one non-volatile memory, in which is stored during manufacture of the multi-die chip assembly, an allowed range of a result of a function having at least two arguments for each reference circuit a value of the frequency of the local reference circuit as manufactured, and a value of the frequency of the distributed circuit as manufactured, at least one element of the plurality of memories being disposed in each die including the elements of the local reference circuit. Related methods, apparatus, and systems are also described. | 03-12-2015 |
20150220475 | DEVICE IDENTIFICATION GENERATION IN ELECTRONIC DEVICES TO ALLOW EXTERNAL CONTROL OF DEVICE IDENTIFICATION FOR BUS COMMUNICATIONS IDENTIFICATION, AND RELATED SYSTEMS AND METHODS - Device identification generation in electronic devices to allow external control, such as selection or reprogramming, of device identification for bus communications identification, is disclosed. In this manner, device identifications of electronic devices coupled to a common communications bus in a system can be selected or reprogrammed to ensure they are unique to avoid bus communications collisions. In certain aspects, to select or reprogram a device identification in an electronic device, an external source can be electrically coupled to the electronic device. The external source closes a circuit with a device identification generation circuit in the electronic device. The closed circuit provides a desired electrical characteristic detectable by the device identification generation circuit. The device identification generation circuit is configured to generate a device identification as a function of the detected electrical characteristics of the closed circuit from the external source. | 08-06-2015 |
20150371690 | TIME-CONSTRAINED DATA COPYING BETWEEN STORAGE MEDIA - Time-constrained data copying between storage media is disclosed. When an electronic device is engaged in real-time operations, multiple data blocks may need to be copied from one storage medium to another storage medium within certain time constraints. In this regard, a data port is operatively controlled by a plurality of registers of a first register bank. The plurality of registers is copied from the first register bank to a second register bank within a temporal limit and while the data port remains under control of the plurality of registers being copied. By copying the plurality of registers within the temporal limit, it is possible to prevent operational interruption in the data port and reduce bandwidth overhead associated with the register copying operation. | 12-24-2015 |