Patent application number | Description | Published |
20080230917 | METHOD OF FABRICATING TWO-STEP SELF-ALIGNED CONTACT - A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region therein. Next, a lower hole corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper hole self-aligned to and communicated with the lower hole is formed in the second dielectric layer, wherein the upper hole and the lower hole constitute a self-aligned contact hole. Afterwards, the self-aligned contact hole is filled with a conductive layer. | 09-25-2008 |
20100073671 | ALIGNMENT MARK AND DEFECT INSPECTION METHOD - A defect inspection method is disclosed. A first type defect inspection system is used to perform a first defect inspection by aligning to an alignment mark on a wafer as a reference point for the first defect inspection. A fabrication process is performed on the wafer thereafter, and a second defect inspection is performed by using a second type defect inspection system to align the alignment mark on the wafer as the reference point for the second defect inspection. | 03-25-2010 |
20100213554 | GATE STRUCTURE AND METHOD FOR TRIMMING SPACERS - A gate structure includes a gate disposed on a substrate, a first spacer disposed on the substrate and surrounding the gate and a second spacer disposed on the first spacer and surrounding the gate, the second spacer is lower than the first spacer. | 08-26-2010 |
20100308220 | INSPECTION STRUCTURE AND METHOD FOR IN-LINE MONITORING WAFER - The method for in-line monitoring a wafer is described as follows. A wafer is provided, and at least one inspection structure is then formed on the wafer in the following steps. An N-well region and a P-well region are formed in the wafer, wherein the N-well region and the P-well region are separated from each other. A gate on each of the N-well region and the P-well region is formed. A P-type doped region is respectively formed in the N-well region and in the P-well region at both sides of the gates. A first contact plug is formed on each P-type doped region, and second contact plug is formed on each gate. Afterwards, a defect inspection is conducted utilizing an electron beam inspection (EBI) system, such that a short between each first contact plug and each gate is determined. | 12-09-2010 |
20100327451 | ALIGNMENT MARK - An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region disposed in the first type well; a dielectric layer disposed on the semiconductor substrate to cover the first type well and the second type doping region; and a plurality of conductive plugs formed in the dielectric layer for connecting to the second type doping region. | 12-30-2010 |
20110143511 | Method of fabricating n-channel metal-oxide semiconductor transistor - A method of fabricating an NMOS transistor, in which, an epitaxial silicon layer is formed before a salicide process is performed, then a nickel layer needed for the salicide process is formed, and, thereafter, a rapid thermal process is performed to allow the nickel layer to react with the epitaxial silicon layer and the silicon substrate under the epitaxial silicon layer to form a nickel silicide layer. | 06-16-2011 |
20120132996 | STRAINED SILICON STRUCTURE - A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance. | 05-31-2012 |
20120248511 | SEMICONDUCTOR STRUCTURE AND METHOD FOR SLIMMING SPACER - A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer. | 10-04-2012 |
20130183803 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE - A method for manufacturing a semiconductor structure is provided. The method includes following steps. A patterned gate layer is formed on a semiconductor substrate. A compensation layer is formed on the semiconductor substrate outside the patterned gate layer. A trench is formed in the compensation layer and the semiconductor substrate. An epitaxial layer is formed in the trench. The step for forming the compensation layer is between the step for forming the patterned gate layer and the step for forming the epitaxial layer. | 07-18-2013 |
20130288446 | SEMICONDUCTOR STRUCTURE AND METHOD FOR SLIMMING SPACER - A semiconductor structure including a substrate and a gate structure disposed on the substrate is disclosed. The gate structure includes a gate dielectric layer disposed on the substrate, a gate material layer disposed on the gate dielectric layer and an outer spacer with a rectangular cross section. The top surface of the outer spacer is lower than the top surface of the gate material layer. | 10-31-2013 |
20130292775 | STRAINED SILICON STRUCTURE - A strained silicon substrate structure includes a first transistor and a second transistor disposed on a substrate. The first transistor includes a first gate structure and two first source/drain regions disposed at two sides of the first gate structure. A first source/drain to gate distance is between each first source/drain region and the first gate structure. The second transistor includes a second gate structure and two source/drain doped regions disposed at two side of the second gate structure. A second source/drain to gate distance is between each second source/drain region and the second gate structure. The first source/drain to gate distance is smaller than the second source/drain to gate distance. | 11-07-2013 |
Patent application number | Description | Published |
20130089962 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. A gate structure is formed on the substrate. A spacer is formed on the substrate beside the gate structure. The spacer includes a first spacer and a second spacer located on the external surface of the first spacer. A first etching process is performed to etch and form at least a recess in the substrate beside the spacer and entirely remove the second spacer. The etching rate of the first etching process to the first spacer is lower than the etching rate of the first etching process to the second spacer. An epitaxial layer is formed in the recess. | 04-11-2013 |
20130171789 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes providing a substrate having a first gate structure and a second gate structure formed thereon; blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate; performing a first ion implantation to form first light-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure; and performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure; wherein at least one of the first ion implantation and the second ion implantation is performed to penetrate through the seal layer. | 07-04-2013 |
20130273706 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer. | 10-17-2013 |
20130341685 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer. | 12-26-2013 |