Patent application number | Description | Published |
20090221766 | STEREOSELECTIVE REDUCTION OF A MORPHINONE - A synthetic method is provided, wherein the method comprises stereoselectively reducing a ketone of a morphinone to form a reduced morphinone and optionally covalently attaching a water soluble polymer to the reduced morphinone. | 09-03-2009 |
20100305147 | CHEMICALLY MODIFIED SMALL MOLECULES - The invention provides small molecule drugs that are chemically modified by covalent attachment of a water-soluble oligomer obtained from a monodisperse or bimodal water-soluble oligomer composition. A conjugate of the invention, when administered by any of a number of administration routes, exhibits a reduced biological membrane crossing rate as compared to the biological membrane crossing rate of the small molecule drug not attached to the water-soluble oligomer. | 12-02-2010 |
20110105438 | Oligomer-Foscarnet Conjugates - The invention relates to (among other things) oligomer-foscarnet conjugates and related compounds. A conjugate of the invention, when administered by any of a number of administration routes, exhibits advantages over previously administered un-conjugated foscarnet compounds. | 05-05-2011 |
20110269677 | Oligomer-Protease Inhibitor Conjugates - The invention provides protease inhibitors that are chemically modified by covalent attachment of a water-soluble oligomer. A conjugate of the invention, when administered by any of a number of administration routes, exhibits characteristics that are different from the protease inhibitors not attached to the water-soluble oligomer. | 11-03-2011 |
20120238621 | Oligomer-Calcimimetic Conjugates and Related Compounds - The invention relates to (among other things) oligomer-calcimimetic conjugates and related compounds. A conjugate of the invention, when administered by any of a number of administration routes, exhibits advantages over previously administered compounds. | 09-20-2012 |
20130018190 | STEREOSELECTIVE REDUCTION OF A MORPHINONE - A synthetic method is provided, wherein the method comprises stereoselectively reducing a ketone of a morphinone to form a reduced morphinone and optionally covalently attaching a water soluble polymer to the reduced morphinone. | 01-17-2013 |
20140303403 | CHEMICALLY MODIFIED SMALL MOLECULES - Methods of modifying the rate of systemic absorption of a drug administered to a subject by a pulmonary route, the method comprising covalently conjugating a hydrophilic polymer to a drug, wherein the drug has a half-life of elimination from the lung of less than about 180 minutes, to form a drug-polymer conjugate, wherein the drug-polymer conjugate has a net hydrophilic character and a weight average molecular weight of from about 50 to about 20,000 Daltons, and wherein the half-life of elimination from the lung of the drug-polymer conjugate is at least about 1.5-fold greater than the half-life of elimination from the lung of the drug, wherein the half-life of elimination from the lung is measured by bronchoalveolar lavage followed by assaying residual lung material. | 10-09-2014 |
20150197470 | CHEMICALLY MODIFIED SMALL MOLECULES - Methods of modifying the rate of systemic absorption of a drug administered to a subject by a pulmonary route, the method comprising covalently conjugating a hydrophilic polymer to a drug, wherein the drug has a half-life of elimination from the lung of less than about 180 minutes, to form a drug-polymer conjugate, wherein the drug-polymer conjugate has a net hydrophilic character and a weight average molecular weight of from about 50 to about 20,000 Daltons, and wherein the half-life of elimination from the lung of the drug-polymer conjugate is at least about 1.5-fold greater than the half-life of elimination from the lung of the drug, wherein the half-life of elimination from the lung is measured by bronchoalveolar lavage followed by assaying residual lung material. | 07-16-2015 |
Patent application number | Description | Published |
20100320476 | VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND DIODES HAVING GRADED DOPED REGIONS AND METHODS OF MAKING - Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices have graded p-type semiconductor layers and/or regions formed by epitaxial growth. The methods do not require ion implantation. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications. | 12-23-2010 |
20100320530 | METHODS OF MAKING VERTICAL JUNCTION FIELD EFFECT TRANSISTORS AND BIPOLAR JUNCTION TRANSISTORS WITHOUT ION IMPLANTATION AND DEVICES MADE THEREWITH - Methods of making semiconductor devices such as vertical junction field effect transistors (VJFETs) or bipolar junction transistors (BJTs) are described. The methods do not require ion implantation. The VJFET device has an epitaxially regrown n-type channel layer and an epitaxially regrown p-type gate layer as well as an epitaxially grown buried gate layer. Devices made by the methods are also described. | 12-23-2010 |
20120223330 | SEMICONDUCTOR DEVICE HAVING HIGH PERFORMANCE CHANNEL - Semiconductor devices having a high performance channel and method of fabrication thereof are disclosed. Preferably, the semiconductor devices are Metal-Oxide-Semiconductor (MOS) devices, and even more preferably the semiconductor devices are Silicon Carbide (SiC) MOS devices. In one embodiment, a semiconductor device includes a SiC substrate of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, and a surface diffused channel of the second conductivity type formed at the surface of semiconductor device between the first and second wells. A depth and doping concentration of the surface diffused channel are controlled to provide increased carrier mobility for the semiconductor device as compared to the same semiconductor device without the surface diffused channel region when in the on-state while retaining a turn-on, or threshold, voltage that provides normally-off behavior. | 09-06-2012 |
20120280252 | Field Effect Transistor Devices with Low Source Resistance - A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region. | 11-08-2012 |
20120280270 | Field Effect Transistor Devices with Low Source Resistance - A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region. | 11-08-2012 |
20120326163 | SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL MOBILITY AND DRY CHEMISTRY PROCESSES FOR FABRICATION THEREOF - Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device. | 12-27-2012 |
20120329216 | WET CHEMISTRY PROCESSES FOR FABRICATING A SEMICONDUCTOR DEVICE WITH INCREASED CHANNEL MOBILITY - Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device. | 12-27-2012 |
20130026493 | SIC DEVICES WITH HIGH BLOCKING VOLTAGE TERMINATED BY A NEGATIVE BEVEL - The present disclosure relates to a Silicon Carbide (SiC) semiconductor device having both a high blocking voltage and low on-resistance. In one embodiment, the semiconductor device has a blocking voltage of at least 10 kilovolts (kV) and an on-resistance of less than 10 milli-ohms centimeter squared (mΩ·cm | 01-31-2013 |
20130146894 | BIPOLAR JUNCTION TRANSISTOR STRUCTURE FOR REDUCED CURRENT CROWDING - The present disclosure relates to a bipolar junction transistor (BJT) structure that significantly reduces current crowding while improving the current gain relative to conventional BJTs. The BJT includes a collector, a base region, and an emitter. The base region is formed over the collector and includes at least one extrinsic base region and an intrinsic base region that extends above the at least one extrinsic base region to provide a mesa. The emitter is formed over the mesa. The BJT may be formed from various material systems, such as the silicon carbide (SiC) material system. In one embodiment, the emitter is formed over the mesa such that essentially none of the emitter is formed over the extrinsic base regions. Typically, but not necessarily, the intrinsic base region is directly laterally adjacent the at least one extrinsic base region. | 06-13-2013 |
20130264581 | BIPOLAR JUNCTION TRANSISTOR WITH IMPROVED AVALANCHE CAPABILITY - A bipolar junction transistor (BJT), which includes a collector layer, a base layer on the collector layer, an emitter layer on the base layer, and a recess region embedded in the collector layer, is disclosed. A base-collector plane is between the base layer and the collector layer. The recess region is may be below the base-collector plane. Further, the recess region and the base layer are a first type of semiconductor material. By embedding the recess region in the collector layer, the recess region and the collector layer form a first P-N junction, which may provide a point of avalanche for the BJT. Further, the collector layer and the base layer form a second P-N junction. By separating the point of avalanche from the second P-N junction, the BJT may avalanche robustly, thereby reducing the likelihood of avalanche induced failures, particularly in silicon carbide (SiC) BJTs. | 10-10-2013 |
20140070230 | USING A CARBON VACANCY REDUCTION MATERIAL TO INCREASE AVERAGE CARRIER LIFETIME IN A SILICON CARBIDE SEMICONDUCTOR DEVICE - A semiconductor die and a process for fabricating the semiconductor die are disclosed. The semiconductor die has a substrate and a silicon carbide (SiC) epitaxial structure on the substrate. The SiC epitaxial structure includes at least a first N-type SiC layer, at least a first P-type SiC layer, and carbon vacancy reduction material, which has been implanted into a surface of the SiC epitaxial structure. Further, the SiC epitaxial structure has been annealed to mobilize the carbon vacancy reduction material to diffuse carbon atoms substantially throughout the SiC epitaxial structure, thereby increasing an average carrier lifetime in the SiC epitaxial structure. | 03-13-2014 |
20140264562 | Field Effect Transistor Devices with Regrown P-Layers - A transistor device includes a drift layer having a first conductivity type, a body layer on the drift layer, the body layer having a second conductivity type opposite the first conductivity type, and a source region on the body layer, the source region having the first conductivity type. The device further includes a trench extending through the source region and the body layer and into the drift layer, a channel layer on the inner sidewall of the trench, the channel layer having the second conductivity type and having an inner sidewall opposite an inner sidewall of the trench, a gate insulator on the inner sidewall of the channel layer, and a gate contact on the gate insulator. | 09-18-2014 |
20140264563 | Field Effect Transistor Devices with Protective Regions - A transistor device includes a first conductivity type drift layer, a second conductivity type first region in the drift layer, a body layer having the second conductivity type on the drift layer including the first region, a source layer on the body layer, and a body contact region that extends through the source layer and the body layer and into the first region. The transistor device further includes a trench through the source layer and the body layer and extending into the drift layer adjacent the first region. The trench has an inner sidewall facing away from the first region. A gate insulator is on the inner sidewall of the trench, and a gate contact is on the gate insulator. | 09-18-2014 |
20140264564 | Field Effect Transistor Devices with Buried Well Protection Regions - A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator. | 09-18-2014 |
20140264579 | Field Effect Transistor Devices with Buried Well Regions and Epitaxial Layers - A method of forming a transistor device includes providing a drift layer having a first conductivity type and an upper surface, forming first regions in the drift layer and adjacent the upper surface, the first regions having a second conductivity type that is opposite the first conductivity type and being spaced apart from one another, forming a body layer on the drift layer including the source regions, forming spaced apart source regions in the body layer above respective ones of the first regions, forming a vertical conduction region in the body layer between the source regions, the vertical conduction region having the first conductivity type and defining channel regions in the body layer between the vertical conduction region and respective ones of the source regions, forming a gate insulator on the body layer, and forming a gate contact on the gate insulator. | 09-18-2014 |
20150021623 | ENHANCED GATE DIELECTRIC FOR A FIELD EFFECT DEVICE WITH A TRENCHED GATE - The present disclosure relates to a silicon carbide (SiC) field effect device that has a gate assembly formed in a trench. The gate assembly includes a gate dielectric that is an dielectric layer, which is deposited along the inside surface of the trench and a gate dielectric formed over the gate dielectric. The trench extends into the body of the device from a top surface and has a bottom and side walls that extend from the top surface of the body to the bottom of the trench. The thickness of the dielectric layer on the bottom of the trench is approximately equal to or greater than the thickness of the dielectric layer on the side walls of the trench. | 01-22-2015 |
20150021742 | Methods of Forming Junction Termination Extension Edge Terminations for High Power Semiconductor Devices and Related Semiconductor Devices - Methods of forming a power semiconductor device having an edge termination are provided in which the power semiconductor device that has a drift region of a first conductivity type is formed on a substrate. A junction termination extension is formed on the substrate adjacent the power semiconductor device, the junction termination extension including a plurality of junction termination zones that are doped with dopants having a second conductivity type. The junction termination zones have different effective doping concentrations. A dopant activation process is performed to activate at least some of the dopants in the junction termination zones. An electrical characteristic of the power semiconductor device is measured. Then, the junction termination extension is etched in order to reduce the effective doping concentration within the junction termination extension. | 01-22-2015 |
20150028351 | Methods of Forming Buried Junction Devices in Silicon Carbide Using Ion Implant Channeling and Silicon Carbide Devices Including Buried Junctions - A semiconductor device structure according to some embodiments includes a silicon carbide substrate having a first conductivity type, a silicon carbide drift layer having the first conductivity type on the silicon carbide substrate and having an upper surface opposite the silicon carbide substrate, and a buried junction structure in the silicon carbide drift layer. The buried junction structure has a second conductivity type opposite the first conductivity type and has a junction depth that is greater than about one micron. | 01-29-2015 |
20150041886 | VERTICAL POWER TRANSISTOR DEVICE - A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift layer. The spreading layer includes a pair of junction implants separated by a junction gate field effect (JFET) region. A gate oxide layer is on top of the spreading layer. The gate contact is on top of the gate oxide layer. Each one of the source contacts are on a portion of the spreading layer separate from the gate oxide layer and the gate contact. The drain contact is on the surface of the substrate opposite the drift layer. | 02-12-2015 |
20150048489 | EDGE TERMINATION TECHNIQUE FOR HIGH VOLTAGE POWER DEVICES - Embodiments of a semiconductor die having a semiconductor device implemented on the semiconductor die and an edge termination structure around a periphery of the semiconductor device and methods of fabricating the same are disclosed. In one embodiment, a semiconductor die includes a semiconductor device and an edge termination structure around a periphery of the semiconductor device, where the edge termination structure includes negative features (e.g., trenches and/or divots) that vary dose in a corresponding edge termination region to approximate a desired dose profile. In one embodiment, the desired dose profile is a substantially decreasing or substantially linearly decreasing dose from an edge of a main junction of the semiconductor device to an edge of the edge termination region. In this manner, electric field crowding at the edge of the main junction of the semiconductor device is substantially reduced, which in turn substantially improves a break-down voltage of the semiconductor device. | 02-19-2015 |
20150084062 | MONOLITHICALLY INTEGRATED VERTICAL POWER TRANSISTOR AND BYPASS DIODE - A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer. | 03-26-2015 |
20150084063 | SEMICONDUCTOR DEVICE WITH A CURRENT SPREADING LAYER - A semiconductor device includes a substrate, a drift layer over the substrate, a spreading layer over the drift layer, and a pair of junction implants in a surface of the spreading layer opposite the drift layer. An anode covers the surface of the spreading layer opposite the drift layer, and a cathode covers a surface of the substrate opposite the drift layer. By including the spreading layer, a better balance can be struck between the on state resistance of the semiconductor device and the peak electric field in the device, thereby improving the performance thereof. | 03-26-2015 |
20150084118 | SEMICONDUCTOR DEVICE INCLUDING A POWER TRANSISTOR DEVICE AND BYPASS DIODE - A semiconductor device includes a vertical FET device and a Schottky bypass diode. The vertical FET device includes a gate contact, a source contact, and a drain contact. The gate contact and the source contact are separated from the drain contact by at least a drift layer. The Schottky bypass diode is coupled between the source contact and the drain contact and monolithically integrated adjacent to the vertical FET device such that a voltage placed between the source contact and the drain contact is distributed throughout the drift layer by the Schottky bypass diode in such a way that a voltage across each one of a plurality of P-N junctions formed between the source contact and the drain contact within the vertical FET device is prevented from exceeding a barrier voltage of the respective P-N junction. | 03-26-2015 |
20150084119 | LAYOUT CONFIGURATIONS FOR INTEGRATING SCHOTTKY CONTACTS INTO A POWER TRANSISTOR DEVICE - A semiconductor device includes a vertical field-effect-transistor (FET) and a bypass diode. The vertical FET device includes a substrate, a drift layer formed over the substrate, a gate contact and a plurality of source contacts located on a first surface of the drift layer opposite the substrate, a drain contact located on a surface of the substrate opposite the drift layer, and a plurality of junction implants, each of the plurality of junction implants laterally separated from one another on the surface of the drift layer opposite the substrate and extending downward toward the substrate. Each of the one or more bypass diodes are formed by placing a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the plurality of junction implants. | 03-26-2015 |
20150084125 | MONOLITHICALLY INTEGRATED VERTICAL POWER TRANSISTOR AND BYPASS DIODE - A vertical field-effect transistor (FET) device includes a monolithically integrated bypass diode connected between a source contact and a drain contact of the vertical FET device. According to one embodiment, the vertical FET device includes a pair of junction implants separated by a junction field-effect transistor (JFET) region. At least one of the junction implants of the vertical FET device includes a deep well region that is shared with the integrated bypass diode, such that the shared deep well region functions as both a source junction in the vertical FET device and a junction barrier region in the integrated bypass diode. The vertical FET device and the integrated bypass diode may include a substrate, a drift layer over the substrate, and a spreading layer over the drift layer, such that the junction implants of the vertical FET device are formed in the spreading layer. | 03-26-2015 |
20150097226 | FIELD EFFECT DEVICE WITH ENHANCED GATE DIELECTRIC STRUCTURE - A vertically oriented field effect device has a body and an enhance gate structure. The body includes a JFET (junction field effect transistor) region disposed between junction implants that extend into the body from a top surface of the body. The gate structure includes a supplemental gate dielectric, a primary gate dielectric, and a gate contact. The supplemental gate dielectric is formed over the top surface of the body above the JFET region, such that the supplemental dielectric is separated from the junction implants by a gap. The primary gate dielectric is formed over the supplemental gate dielectric, above the gap over the top surface of the body, and over at least a portion of the junction implants. The gate contact is formed over the primary gate dielectric. | 04-09-2015 |
20150102361 | SEMICONDUCTOR DEVICES IN SIC USING VIAS THROUGH N-TYPE SUBSTRATE FOR BACKSIDE CONTACT TO P-TYPE LAYER - A Silicon Carbide (SiC) semiconductor device having back-side contacts to a P-type region and methods of fabrication thereof are disclosed. In one embodiment, an SiC semiconductor device includes an N-type substrate and an epitaxial structure on a front-side of the N-type substrate. The epitaxial substrate includes a P-type layer adjacent to the N-type substrate and one or more additional SiC layers on the P-type layer opposite the N-type substrate. The semiconductor device also includes one or more openings through the N-type substrate that extend from a back-side of the N-type substrate to the P-type layer and a back-side contact on the back-side of the N-type substrate and within the one or more openings such that the back-side contact is in physical and electrical contact with the P-type layer. The semiconductor device further includes front-side contacts on the epitaxial structure opposite the N-type substrate. | 04-16-2015 |
20150263145 | IGBT STRUCTURE FOR WIDE BAND-GAP SEMICONDUCTOR MATERIALS - An IGBT device includes an IGBT stack, a collector contact, a gate contact, and an emitter contact. The IGBT stack includes an injector region, a drift region over the injector region, a spreading region over the drift region, and a pair of junction implants in the spreading region. The spreading region provides a first surface of the IGBT stack, which is opposite the drift region. The pair of junction implants is separated by a channel, and extends from the first surface of the IGBT stack along a lateral edge of the IGBT stack towards the drift region to a first depth, such that the thickness of the spreading region is at least one and a half times greater than the first depth. | 09-17-2015 |
20160005837 | Field Effect Transistor Devices with Buried Well Protection Regions - A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator. | 01-07-2016 |