Patent application number | Description | Published |
20130095644 | PLANARIZATION PROCESS FOR SEMICONDUCTOR DEVICE FABRICATION - The present disclosure provides a method of semiconductor fabrication including forming a dielectric layer is formed on and interposing a first feature and a second feature. A first CMP process is performed on the dielectric layer to removing the dielectric layer from a top surface of the first feature to expose an underlying layer and decreasing a thickness of the dielectric layer disposed on a top surface of the second feature such that a portion of the dielectric layer remains disposed on the top surface of the second feature. Thereafter, a second CMP process is performed which removes the dielectric layer remaining on the top surface of the second feature. | 04-18-2013 |
20130164930 | GATE HEIGHT LOSS IMPROVEMENT FOR A TRANSISTOR - The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure over an iso region of a substrate and a second gate structure over a dense region of the substrate. The dense region has a greater pattern density than the iso region. The first and second gate structures each have a respective hard mask disposed thereon. The method includes removing the hard masks from the first and second gate structures. The removal of the hard mask from the second gate structure causes an opening to be formed in the second gate structure. The method includes performing a deposition process followed by a first polishing process to form a sacrificial component in the opening. The method includes performing a second polishing process to remove the sacrificial component and portions of the first and second gate structures. | 06-27-2013 |
20130192634 | BRUSH CLEANING SYSTEM - A plate with a static charge on a surface is used to clean a brush. The plate uses both static charge and mechanical force to remove particles from the surface of the brush to increase the useful life of the brush. | 08-01-2013 |
20130256659 | REDUCTION OF OCD MEASUREMENT NOISE BY WAY OF METAL VIA SLOTS - The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and an interconnect structure disposed over the substrate. The interconnect structure includes a plurality of interconnect layers. One of the interconnect layers contains: a plurality of metal via slots and a bulk metal component disposed over the plurality of metal via slots. The present disclosure also provides a method. The method includes providing a wafer, and forming a first layer over the wafer. The method includes forming an interconnect structure over the first layer. The forming the interconnect structure includes forming a second interconnect layer over the first layer, and forming a third interconnect layer over the second interconnect layer. The second interconnect layer is formed to contain a plurality of metal via slots and a bulk metal component formed over the plurality of metal via slots. The third interconnect layer contains one or more metal trenches. | 10-03-2013 |
20140367801 | MECHANISM FOR FORMING METAL GATE STRUCTURE - Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate with a metal gate stack formed on the semiconductor substrate, and the metal gate stack includes a metal gate electrode. The semiconductor device also includes a metal oxide layer formed over the metal gate stack and in direct contact with the metal gate electrode, and a thickness of the metal oxide layer is in a range from about 15 Å to about 40 Å. The metal oxide layer has a first portion made of an oxidized material of the metal gate electrode and has a second portion made of a material different from that of the first portion. | 12-18-2014 |
20150024661 | MECHANISMS FOR REMOVING DEBRIS FROM POLISHING PAD - Embodiments of mechanisms for performing a chemical mechanical polishing (CMP) process are provided. A method for performing a CMP process includes polishing a wafer by using a polishing pad. The method also includes applying a cleaning liquid jet on the polishing pad to condition the polishing pad. A CMP system is also provided. | 01-22-2015 |
20150087144 | APPARATUS AND METHOD OF MANUFACTURING METAL GATE SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a semiconductor substrate and forming a structure over the semiconductor substrate. The structure includes a sacrificial dielectric on the semiconductor substrate and a dummy gate over the sacrificial dielectric. The method further includes removing the dummy gate and the sacrificial dielectric from the structure thereby forming a trench. The method further includes filling a metal layer into the trench and covering over a top surface of an inter layer dielectric (ILD). The method also includes performing a chemical mechanical polishing (CMP) to expose the top surface of the ILD and heating the top surface of the ILD. Moreover, the method includes forming an etch stop layer on the top surface of the ILD. | 03-26-2015 |
20150087208 | APPARATUS AND METHOD FOR MANUFACTURING A SEMICONDUCTOR WAFER - In a semiconductor wafer manufacturing apparatus, a rotation module is provided to hold the semiconductor wafer at a plane. The semiconductor wafer is revolved by the rotation module around a first axis. The first axis is substantially perpendicular to the plane. A cleaning module is configured to revolve around a second axis when the cleaning module contacts the surface of the semiconductor wafer. A mechanism is further provided to enable the rotation module and/or the cleaning module to move along a direction substantially perpendicular to the first axis. Consequently, the relative velocities at the contact points between the semiconductor wafer and the cleaning module are changed. Moreover, no relative velocity at any contact point between the semiconductor wafer and the cleaning module is zero or close to zero. | 03-26-2015 |