Patent application number | Description | Published |
20140127886 | Reducing Pattern Loading Effect in Epitaxy - A method includes forming a gate stack over a semiconductor substrate, forming an opening in the semiconductor substrate and adjacent to the gate stack, and performing a first epitaxy to grow a first semiconductor layer in the first opening. An etch-back is performed to reduce a thickness of the first semiconductor layer. A second epitaxy is performed to grow a second semiconductor layer over the first semiconductor layer. The first and the second semiconductor layers have different compositions. | 05-08-2014 |
20150021688 | MOS Devices with Non-Uniform P-type Impurity Profile - An integrated circuit structure include a semiconductor substrate, a gate stack over the semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A silicon germanium region is disposed in the opening, wherein the silicon germanium region has a first p-type impurity concentration. A silicon cap substantially free from germanium is overlying the silicon germanium region. The silicon cap has a second p-type impurity concentration greater than the first p-type impurity concentration. | 01-22-2015 |
20150021696 | MOS Devices Having Epitaxy Regions with Reduced Facets - An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region. | 01-22-2015 |
20150041852 | Modulating Germanium Percentage in MOS Devices - An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region. | 02-12-2015 |
20150048417 | Germanium Barrier Embedded in MOS Devices - An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A third silicon germanium region is over the second silicon germanium region, wherein the third silicon germanium region has a third germanium percentage lower than the second germanium percentage. | 02-19-2015 |
20150061024 | Source and Drain Stressors with Recessed Top Surfaces - An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion. | 03-05-2015 |