Levit-Gurevich
Konstantin Levit-Gurevich US
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20120177249 | METHOD OF DETECTING LOGOS, TITLES, OR SUB-TITLES IN VIDEO FRAMES - Detecting a static graphic object (such as a logo, title, or sub-title) in a sequence of video frames may be accomplished by analyzing each selected one of a plurality of pixels in a video frame of the sequence of video frames. Basic conditions for the selected pixel may be tested to determine whether the selected pixel is a static pixel. When the selected pixel is a static pixel, a static similarity measure and a forward motion similarity measure may be determined for the selected pixel. A temporal score for the selected pixel may be determined based at least in part on the similarity measures. Finally, a static graphic object decision for the selected pixel may be made based at least in part on the temporal score. | 07-12-2012 |
Konstantin Levit-Gurevich, Kiryat-Bialik IL
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20130268742 | CORE SWITCHING ACCELERATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM - An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code executing on the ASMP is analyzed by a binary analysis unit to determine what functions are called by the program code and select which of the cores are to execute the program code, or a code segment thereof. Selection may be made to provide for native execution of the program code, to minimize power consumption, and so forth. Control operations based on this selection may then be inserted into the program code, forming instrumented program code. The instrumented program code is then executed by the ASMP. | 10-10-2013 |
20140019723 | BINARY TRANSLATION IN ASYMMETRIC MULTIPROCESSOR SYSTEM - An asymmetric multiprocessor system (ASMP) may comprise computational cores implementing different instruction set architectures and having different power requirements. Program code for execution on the ASMP is analyzed and a determination is made as to whether to allow the program code, or a code segment thereof to execute on a first core natively or to use binary translation on the code and execute the translated code on a second core which consumes less power than the first core during execution. | 01-16-2014 |
Konstantin Kostya Levit-Gurevich, Kiryat Byalik IL
Patent application number | Description | Published |
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20140095832 | METHOD AND APPARATUS FOR PERFORMANCE EFFICIENT ISA VIRTUALIZATION USING DYNAMIC PARTIAL BINARY TRANSLATION - Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native instructions and a second core, or alternatively only the second processor core consuming less power while executing a second instruction set that excludes portions of the native instruction set. The second core's decoder detects invalid opcodes of the second instruction set. A microcode layer disassembler determines if opcodes should be translated. A translation runtime environment identifies an executable region containing an invalid opcode, other invalid opcodes and interjacent valid opcodes of the second instruction set. An analysis unit determines an initial machine state prior to execution of the invalid opcode. A partial translation of the executable region that includes encapsulations of the translations of invalid opcodes and state recoveries of the machine states is generated and saved to a translation cache memory. | 04-03-2014 |