Lee, ID
Brady D. Lee, Idaho Falls, ID US
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20090215168 | Transcriptional control in alicyclobacillus acidocaldarius and associated genes, proteins, and methods - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 08-27-2009 |
20090269827 | Thermophilic and thermoacidophilic metabolism genes and enzymes from alicyclobacillus acidocaldadarius and related organisms, methods - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 10-29-2009 |
20110275135 | Genetic elements, proteins, and associated methods including application of additional genetic information to gram (+) thermoacidophiles - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 11-10-2011 |
20130029400 | GENETIC ELEMENTS, PROTEINS, AND ASSOCIATED METHODS INCLUDING APPLICATION OF ADDIITNAL GENETIC INFORMATION TO GRAM (+) THERMOACIDOPHILES - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 01-31-2013 |
20140093936 | TYPE II RESTRICTION MODIFICATION SYSTEM METHYLATION SUBUNIT OF ALICYCLOBACILLUS ACIDOCALDARIUS - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 04-03-2014 |
20140273238 | TRANSCRIPTIONAL CONTROL IN ALICYCLOBACILLUS ACIDOCALDARIUS AND ASSOCIATED GENES, PROTEINS, AND METHODS - Isolated and/or purified polypeptides and nucleic acid sequences encoding polypeptides from | 09-18-2014 |
Che-Chi Lee, Boise, ID US
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20120040507 | METHODS OF FORMING A PLURALITY OF CAPACITORS - A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials. The isotropic etching of the second material is conducted selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials. The capacitor electrodes are ultimately incorporated into a plurality of capacitors. | 02-16-2012 |
20130323902 | Methods of Forming a Plurality of Capacitors - A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials. The isotropic etching of the second material is conducted selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials. The capacitor electrodes are ultimately incorporated into a plurality of capacitors. | 12-05-2013 |
Chris Lee, Boise, ID US
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20090037904 | Firmware Installation - A firmware bundle is download to a non-operational storage area without changing a live copy of firmware in a device. The firmware bundle is downloaded in order to reboot the device to deploy one or more downloaded firmware packages from the non-operational storage area to the device, launch an Early Boot Installer manager to spawn and monitor the status of one or more Early Boot Installer processes contained in the firmware bundle download, determine in parallel whether a firmware install to one or more subsystems of the device is desire, and install the downloaded firmware package in parallel to one or more subsystems of the device. | 02-05-2009 |
Derek Lee, Boise, ID US
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20080251887 | SERIAL SYSTEM FOR BLOWING ANTIFUSES - A serial system and method for blowing antifuses are disclosed. One embodiment of antifuse system includes a plurality of latch devices connected in series from input to output. The system also includes a plurality of antifuses. The antifuses are configured to receive an output signal from a corresponding one of the latch devices. The plurality of latch devices includes a plurality of D flip-flops connected in series. Each of the D flip-flops is configured to receive an output signal from an immediately previous D flip-flop in the serial data flow and to provide an output signal to an immediately subsequent D flip-flop in the flow. In addition, the serial system provides self-detective antifuses, thus creating reliable electrical paths while saving antifuse blowing current resources and time. | 10-16-2008 |
Hong-Wei Lee, Meridian, ID US
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20090127442 | Anti-resonant reflecting optical waveguide for imager light pipe - An anti-resonant reflecting optical waveguide structure for reducing optical crosstalk in an image sensor and method of forming the same. The method includes forming a trench within a plurality of material layers and over a photo-conversion device. The trench is vertically aligned with the photo-conversion device and is filled with materials of varying refractive indices to form an anti-resonant reflecting optical waveguide structure. The anti-resonant reflecting optical waveguide structure has a core and at least two cladding structures. The cladding structure in contact with the core has a refractive index that is higher than the refractive index of the core and the refractive index of the other cladding structure. The cladding structures act as Fabry-Perot cavities for light propagating in the transverse direction, such that light entering the anti-resonant reflecting optical waveguide structure remains confined to the core. This reduces the chance of photons impinging upon neighboring photo-conversion devices. | 05-21-2009 |
20110006193 | ANTI-RESONANT REFLECTING OPTICAL WAVEGUIDE FOR IMAGER LIGHT PIPE - An anti-resonant reflecting optical waveguide structure for reducing optical crosstalk in an image sensor and method of forming the same. The method includes forming a trench within a plurality of material layers and over a photo-conversion device. The trench is vertically aligned with the photo-conversion device and is filled with materials of varying refractive indices to form an anti-resonant reflecting optical waveguide structure. The anti-resonant reflecting optical waveguide structure has a core and at least two cladding structures. The cladding structure in contact with the core has a refractive index that is higher than the refractive index of the core and the refractive index of the other cladding structure. The cladding structures act as Fabry-Perot cavities for light propagating in the transverse direction, such that light entering the anti-resonant reflecting optical waveguide structure remains confined to the core. This reduces the chance of photons impinging upon neighboring photo-conversion devices. | 01-13-2011 |
Jeunghoon Lee, Boise, ID US
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20140272972 | ENHANCED DNA SENSING VIA CATALYTIC AGGREGATION OF GOLD NANOPARTICLES BY DNA HYBRIDIZATION CHAIN REACTION - The present invention provides compositions and methods for colorimetric detection schemes for detecting a variety of biomolecules. The compositions and methods employ DNA hybridization chain reaction for catalytic aggregation of gold nanoparticles. In this catalytic aggregation scheme, a single target DNA strand triggers the formation of multiple inter-particle linkages in contrast to the single linkage formed in conventional direct aggregation schemes. | 09-18-2014 |
Ji Soo Lee, Boise, ID US
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20090141145 | ANTI-ECLIPSING CIRCUIT FOR IMAGE SENSORS - An anti-eclipse circuit of an image pixel includes a clamping circuit for pulling up a voltage of a reset signal output by the pixel and an eclipse detection circuit for controllably coupling the clamping circuit output to the output of the pixel. The clamping circuit includes a source follower transistor and a switching transistor. The eclipse detection circuit includes a comparator that is operated to detect an eclipse condition. The eclipse detection circuit outputs a control signal to cause the switching transistor to conduct only when a eclipse condition is detected while the pixel is outputting a reset signal. | 06-04-2009 |
John K. Lee, Boise, ID US
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20110223761 | METHODS FOR FABRICATING CONTACTS OF SEMICONDUCTOR DEVICE STRUCTURES AND METHODS FOR DESIGNING SEMICONDUCTOR DEVICE STRUCTURES - Methods for fabricating contacts of semiconductor device structures include forming a dielectric layer over a semiconductor substrate with active-device regions spaced at a first pitch, forming a first plurality of substantially in-line apertures over every second active-device region of the active-device regions, and forming a second plurality of substantially in-line apertures laterally offset from apertures of the first plurality over active-device regions over which apertures of the first plurality are not located. Methods for designing semiconductor device structures include forming at least two laterally offset sets of contacts over a substrate including active-device regions at a first pitch, the contacts being formed at a second pitch that is about twice the first pitch. | 09-15-2011 |
Jong-Won Lee, Boise, ID US
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20130299767 | DEPOSITING TITANIUM SILICON NITRIDE FILMS FOR FORMING PHASE CHANGE MEMORIES - Organometallic precursors may be utilized to form titanium silicon nitride films that act as heaters for phase change memories. By using a combination of TDMAT and TrDMASi, for example in a metal organic chemical vapor deposition chamber, a relatively high percentage of silicon may be achieved in reasonable deposition times, in some embodiments. In one embodiment, two separate bubblers may be utilized to feed the two organometallic compounds in gaseous form to the deposition chamber so that the relative proportions of the precursors can be readily controlled. | 11-14-2013 |
20130344676 | PHASE CHANGE MEMORY INCLUDING OVONIC THRESHOLD SWITCH WITH LAYERED ELECTRODE AND METHODS FOR FORMING THE SAME - Erosion of chalcogenides in phase change memories using ovonic threshold switch selectors can be reduced by controlling columnar morphology in electrodes used in the ovonic threshold switch. The columnar morphology may cause cracks to occur which allow etchants used to etch the ovonic threshold switch to sneak through the ovonic threshold switch and to attack chalcogenides, either in the switch or in the memory element. In one embodiment, the electrode may be split into two metal nitride layers separated by an intervening metal layer. | 12-26-2013 |
20150160146 | MATERIAL TEST STRUCTURE - Material test structures having cantilever portions and methods of forming the same are described herein. As an example, a method of forming a material test structure includes forming a number of electrode portions in a first dielectric material, forming a second dielectric material on the first dielectric material, wherein the second dielectric material includes a first cantilever portion and a second cantilever portion, and forming a test material on the number of electrode portions, the first dielectric material, and the second dielectric material. | 06-11-2015 |
20150280118 | REPLACEMENT MATERIALS PROCESSES FOR FORMING CROSS POINT MEMORY - Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material. | 10-01-2015 |
20150332762 | MEMORY ARRAY PLANE SELECT - Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material. | 11-19-2015 |
June Lee, Boise, ID US
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20090300311 | SELECTIVE REGISTER RESET - The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an indication of a die and a plane associated with at least one address cycle. Such a method can also include selectively resetting a particular register of a number of registers, the particular register corresponding to the plane and the die. | 12-03-2009 |
M. Hope Lee, Idaho Falls, ID US
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20130199996 | GROUND WATER REMEDIATION USING HUMATE ENHANCED AEROBIC COMETABOLISM - A process of bioremediation of chlorinated solvents is provided. The process involves stimulating a microbial biomass of bacteria having oxygenase activity through the introduction of natural organic matter, such as a soluble humate, into a contaminated aquifer. The resulting increase in bacterial biomass results in the cometabolism of chlorinated solvents. The process allows remediation of a contaminated aquifer under aerobic conditions. | 08-08-2013 |
Minsoo Lee, Boise, ID US
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20140003148 | THREE DIMENSIONAL NAND FLASH WITH SELF-ALIGNED SELECT GATE | 01-02-2014 |
20140167131 | THREE DIMENSIONAL MEMORY - A method to fabricate a three dimensional memory structure may include creating a stack of layers including a conductive source layer, a first insulating layer, a select gate source layer, and a second insulating layer, and an array stack. A hole through the stack of layers may then be created using the conductive source layer as a stop-etch layer. The source material may have an etch rate no faster than 33% as fast as an etch rate of the insulating material for the etch process used to create the hole. A pillar of semiconductor material may then fill the hole, so that the pillar of semiconductor material is in electrical contact with the conductive source layer. | 06-19-2014 |
20150348790 | METHODS AND APPARATUSES INCLUDING MEMORY CELLS WITH AIR GAPS AND OTHER LOW DIELECTRIC CONSTANT MATERIALS - Various embodiments include methods of forming memory cells. In one embodiment, a first dielectric material and a second dielectric material are formed on a substrate. A conductive material is formed between the first dielectric material and the second dielectric material. An opening is formed through the first dielectric material, the second dielectric material, and the conductive material. The conductive material is recessed laterally from the opening to form a recessed control gate and to expose portions of the first dielectric material and the second dielectric material. Portions of a third dielectric material are formed over the exposed portions of the first dielectric material and the second dielectric material and a charge storage element is formed between the portions of the third dielectric material and adjacent to the recessed control gate. Portions of the third dielectric material are substantially removed. Additional methods, as well as apparatuses, are disclosed. | 12-03-2015 |
20150371925 | THROUGH ARRAY ROUTING FOR NON-VOLATILE MEMORY - Technologies for routing access lines in non-volatile memory are described. In some embodiments the technologies include forming one or more through array vias in a portion of a memory array in a non-volatile memory, such as in an array region or peripheral region, one or more access lines may be routed through the through array via, instead of within a region above or below an array or peripheral region of the memory array. This can enable alternative routing configurations, and may enable additional access lines to be routed without increasing or substantially increasing the block height of the non-volatile memory. Non-volatile memory employing such technologies is also described. | 12-24-2015 |
Nathan Lee, Boise, ID US
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20150054993 | ARRAY CAMERAS WITH LIGHT BARRIERS - An imaging system such as an array camera may include an array of image sensors. The image sensors may each include an array of image pixels formed in a common image sensor substrate. A protective glass cover layer may be provided over the array of image sensors. The cover layer may be attached to the image sensor substrate using an adhesive. The adhesive may be formed on the image sensor substrate in a grid-like pattern in between adjacent image sensors in the array. A light blocking material may be formed on the adhesive grid to minimize optical crosstalk between neighboring image sensors. The light blocking material may fill or partially fill a trench in the adhesive, may coat the outer surfaces of the adhesive, and/or may coat the inner surfaces of the adhesive. If desired, light barriers may also be formed in openings in the glass cover layer. | 02-26-2015 |
20150062420 | IMAGE SENSORS WITH INTERCONNECTS IN COVER LAYER - An image sensor die may include a pixel array formed in an image sensor substrate and covered by a transparent cover layer. The transparent cover layer may be attached to the image sensor substrate using adhesive. Electrical interconnect structures such as conductive vias may be formed in the transparent cover layer and may be used in conveying electrical signals between the image sensor and a printed circuit board. The conductive vias may have one end coupled to a bond pad on the upper surface of the transparent cover layer and an opposing end coupled to a bond pad on the upper surface of the image sensor substrate. The conductive vias may pass through openings that extend through the transparent cover layer and the adhesive. Conductive structures such as wire bonds, stud bumps, or solder balls may be coupled to the bond pads on the surface of the transparent cover layer. | 03-05-2015 |
Phil W. Lee, Boise, ID US
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20120185738 | DETERMINING LOCATION OF ERROR DETECTION DATA - Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of memory cells includes determining a location of where to store error detection data for data to be stored across a plurality of memory units, including the memory unit having the bad group, based at least partially on a location of the bad group and storing the error detection data in the determined location. | 07-19-2012 |
20140149804 | DETERMINING LOCATION OF ERROR DETECTION DATA - Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of memory cells includes determining a location of where to store error detection data for data to be stored across a plurality of memory units, including the memory unit having the bad group, based at least partially on a location of the bad group and storing the error detection data in the determined location. | 05-29-2014 |
Roger Lee, Eagle, ID US
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20110291190 | System and method for integrated circuits with cylindrical gate structures - A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel. | 12-01-2011 |
20120032732 | HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING - A method for making an integrated circuit includes at least a tri-gate FinFET and a dual-gate FinFET. The method includes providing a semiconductor on insulator (SOI) substrate. The method also includes implanting impurities into the substrate for adjusting a threshold voltage. The method provides a nitride film overlying a surface region of the substrate and selectively etches the silicon nitride film to form a nitride cap region. The method etches the silicon layer to form a first and a second silicon fin regions. The nitride cap region is maintained on a portion of a surface region of the first silicon fin region. The method includes forming a gate dielectric, depositing a polysilicon film, and planarizing the polysilicon film by chemical mechanical polishing (CMP) using the nitride cap region as a polish stop. The method etches the polysilicon film to form gate electrodes. The method forms elevated source and drain regions. | 02-09-2012 |
20150024559 | SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES - A system and method for integrated circuits with surrounding gate structures are disclosed. The integrated circuits system includes a transistor having a gate all around cylindrical (GAAC) nanowire channel with an interposed dielectric layer. The cylindrical nanowire channel being in a middle section of a semiconductor wire pattern connects the source and drain region positioned at the two opposite end sections of the same wire pattern. A method is provided for manufacturing the integrate circuits system with a GAAC transistor including forming an SOI layer wire pattern on the buried oxide layer of an SOI wafer; forming a cavity underneath the middle section of the wire pattern and shaping the middle section to cylindrically shaped channel; forming a gate electrode surrounding the cylindrical channel region with an interposed gate dielectric layer, the gate electrode being positioned on the buried oxide layer vertically towards the wire pattern; forming the source/drain regions at the two opposite end sections of the wire pattern on either sides of the gate electrode and channel. | 01-22-2015 |
Roger R. Lee, Boise, ID US
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20090311843 | CONTAINER CAPACITOR STRUCTURE AND METHOD OF FORMATION THEREOF - Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures, which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via. | 12-17-2009 |
Si-Woo Lee, Boise, ID US
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20160104709 | PASSING ACCESS LINE STRUCTURE IN A MEMORY DEVICE - A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins. | 04-14-2016 |