Lee, Hsin-Chu City
Chang-Sheng Lee, Hsin-Chu City TW
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20150099315 | MECHANISMS FOR MONITORING IMPURITY IN HIGH-K DIELECTRIC FILM - Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment. | 04-09-2015 |
20150348856 | PLANARIZATION METHOD, METHOD FOR POLISHING WAFER, AND CMP SYSTEM - A planarization method is provided. The planarization method includes providing a wafer, in which the wafer includes a work function layer, a surface layer formed on the work function layer and oxidized from the work function layer, and a planarization layer disposed on or above the surface layer, performing a chemical-mechanical planarization (CMP) process on the planarization layer, providing an incident light to a surface of the wafer under the CMP process, detecting absorption of the incident light by the surface layer; and stopping the CMP process in response to an increase in the detected absorption of the incident light. | 12-03-2015 |
Chia-Yi Lee, Hsin-Chu City TW
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20090160794 | Method for Scroll Control on Window by a Touch Panel - A method for scroll control on a window by a touch panel includes detecting the number of objects touching on the touch panel, enabling a scrolling function when the number of the objects is a first predetermined number, and detecting whether at least one of the objects is touching on an edge of the touch panel after the scrolling function is enabled, if at least one of the objects is touching on the edge of the touch panel, automatically performing a corresponding one of a vertical scrolling and a horizontal scrolling toward a positional direction of the edge. The method is more conveniently operative to the user. | 06-25-2009 |
Ching-Hone Lee, Hsin-Chu City TW
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20100289552 | SYSTEMS INCLUDING LEVEL SHIFTER HAVING VOLTAGE DISTRIBUTOR - An exemplary embodiment of such a system includes: a level shifter operative to transform an input signal into an output signal, the level shifter includes: a voltage distributor operative to receive the input signal and distribute potential levels at a first node and a second node to respectively output a first signal and a second signal, and the voltage distributor includes: a current limiter, operative to provide a limited current passing through the first node; a switch, operative to selectively establish an electrical connection between the first node and the second node; and a first transistor having a first electrode, a second electrode, and a first control electrode, wherein the first electrode is connected to the second node, the second electrode is utilized to receive the input signal, and the first control electrode is coupled to the first node; and an output circuit, operative to generate the output signal. | 11-18-2010 |
Chung-Ju Lee, Hsin-Chu City TW
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20130069234 | STRUCTURE AND METHOD FOR TUNABLE INTERCONNECT SCHEME - The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively. | 03-21-2013 |
20150093902 | Self-Aligned Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a plurality of spacers over a first hard mask layer to form a first mask pattern, and forming a first photoresist over the plurality of spacers. The method further includes patterning the first photoresist to form a second mask pattern, and patterning the first hard mask layer using the first mask pattern and the second mask pattern in a same patterning step. | 04-02-2015 |
Chun-Hung Lee, Hsin-Chu City TW
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20150348796 | Nano Wire Structure and Method for Fabricating the Same - A device comprises a first group of nanowires having a first pattern, a second group of nanowires having a second pattern, a third group of nanowires having a third pattern and a fourth group of nanowires having a fourth pattern, wherein the first pattern, the second pattern, the third pattern and the fourth pattern form a repeating pattern. | 12-03-2015 |
Chun-Yu Lee, Hsin-Chu City TW
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20100123853 | LIQUID CRYSTAL DISPLAY PANEL AND APPARATUS COMPRISING THE SAME - A liquid crystal display panel and an apparatus comprising the same are disclosed. The apparatus comprises the liquid crystal display panel and a backlight module. The backlight module includes a lighting area. The liquid crystal display panel is disposed opposite to the backlight module. The liquid crystal display panel comprises a first substrate facing the backlight module and a first polarizer disposed at the outside of the first substrate. The first polarizer covers the lighting area of the backlight module, but does not exceed or flush with the first substrate. | 05-20-2010 |
Hsuan-Hsien Lee, Hsin-Chu City TW
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20100177209 | Interactive device capable of improving image processing - An interactive device for improving image processing. The interactive device includes a processing module and a controller. The processing module includes a substrate, an image sensor formed on the substrate for generating a plurality of pixel signals, a calculation unit formed on the substrate for calculating at least one motion vector based on the plurality of pixel signals, and a transmission interface formed on the substrate for serially outputting the motion vector. The controller is used for controlling operation of the interactive device based on the motion vector output by the transmission interface | 07-15-2010 |
Hui Yu Lee, Hsin-Chu City TW
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20130134553 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES - Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise. | 05-30-2013 |
20130290916 | SYSTEM AND METHOD FOR REDUCING LAYOUT-DEPENDENT EFFECTS - A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium. | 10-31-2013 |
20140001609 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES | 01-02-2014 |
20140130001 | Method of Reducing Parasitic Mismatch - A method of reducing parasitic mismatches comprises generating a first net list file from a first layout through a resistance-inductance-capacitance (RLC) extraction mechanism using a first simulation tool, performing a V/I test on a network through a second simulation tool, determining whether a mismatch exists based upon a result of the V/I test and modifying a connection trace of the network to generate a second layout. | 05-08-2014 |
20140245242 | VARIATION FACTOR ASSIGNMENT - One or more embodiments of techniques or systems for variation factor assignment for a device are provided herein. In some embodiments, a peripheral environment is determined for a device. A peripheral environment is a layout structure or an instance. When the peripheral environment is the layout structure, a variation factor is assigned to the device based on an architecture associated with the layout structure. When the peripheral environment is the instance, the variation factor is assigned to the device based on a bounding window created for the instance. In this manner, variation factor assignment is provided, such that a first device within a first block of a die has a different variation factor than a second device within a second block of the die, thus giving finer granularity to variation factor assignments. | 08-28-2014 |
20140282308 | METHOD OF RADIO-FREQUENCY AND MICROWAVE DEVICE GENERATION - The present disclosure relates to an apparatus and method to generate a device library, along with layout versus schematic (LVS) and parasitic extraction set-up files for connecting with official tools of a design window supported by a process design kit (PDK). The device library comprises passive devices which can be utilized at any point in an end-to-end design flow from pre-layout verification to post-layout verification of an integrated circuit design. The device library allows for a single schematic view for pre-layout verification but also post-layout verification, thus allowing for pole or pin comparison, and prevents double-counting of parasitic effects from passive design elements by directly instantiating a device from the device library for a verification step. An LVS and parasitic extraction graphical user interface (GUI) allows for incorporation of the generated device library into a pre-existing PDK without any modification to the PDK. Other devices and methods are also disclosed. | 09-18-2014 |
20150121317 | MULTI-PATTERNING SYSTEM AND METHOD - A non-transitory, computer readable storage medium is encoded with computer program instructions, such that, when the computer program instructions are executed by a computer, the computer performs a method. The method generates mask assignment information for forming a plurality of patterns on a layer of an integrated circuit (IC) by multipatterning. The mask assignment information includes, for each of the plurality of patterns, a mask assignment identifying which of a plurality of masks is to be used to form that pattern, and a mask assignment lock state for that pattern. User inputs setting the mask assignment of at least one of the plurality of patterns, and its mask assignment lock state are received. A new mask assignment is generated for each of the plurality of patterns having an “unlocked” mask assignment lock state. | 04-30-2015 |
20150149977 | PARTITIONING METHOD AND SYSTEM FOR 3D IC - A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting. | 05-28-2015 |
Hung-Yu Lee, Hsin-Chu City TW
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20140028552 | IMAGE SENSING METHOD, AND IMAGE SENSING APPARATUS, LIGHT SOURCE DETERMINING SYSTEM UTILIZING THE IMAGE SENSING METHOD - An image detecting method, comprising: controlling a synchronizing controller to transmit a first activating signal to a light source controller; controlling the light source controller to control at least one light source to generate a predetermined radiating pattern, and controlling the light source controller to transmit back a first responding signal to the synchronizing controller when the light source controller receives the first activating signal; and controlling an image sensor to start an image detecting when the synchronizing controller receives the first responding signal. | 01-30-2014 |
Jin-Yuan Lee, Hsin-Chu City TW
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20110309473 | CHIP PACKAGE WITH DIE AND SUBSTRATE - A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure. | 12-22-2011 |
Joon Chok Lee, Hsin-Chu City TW
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20150234483 | DYNAMIC SCALE FOR MOUSE SENSOR RUNAWAY DETECTION - A method for dynamically setting a scale for performing a cross-correlation check between a reference image and a comparison image of a mouse includes: setting a plurality of scale sizes for a cross-correlation check; providing a look up table (LUT) mapping the plurality of scale sizes to a plurality of overlapped areas of the reference image and comparison image and a plurality of predicted locations for the cross-correlation; determining a velocity of motion of the mouse, and using the determined velocity to generate a predicted location; inputting the predicted location to the LUT and mapping to a scale size; and performing the cross-correlation check according to the scale size. | 08-20-2015 |
Ko-Yen Lee, Hsin-Chu City TW
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20110033174 | CONTROL CIRCUIT FOR A VARIABLE FREQUENCY DC MOTOR - The present invention discloses a control circuit for a variable frequency DC motor, the control circuit comprising: a controller, having a voltage sensing input end and a control output end, wherein the control output end is used to deliver an output signal according to the difference between a threshold voltage and the voltage at the voltage sensing input end; a transistor, having a first terminal, a second terminal and a third terminal, wherein the first terminal is coupled to the voltage sensing input end, and the second terminal is coupled to the variable frequency DC motor, and the third terminal is coupled to a reference ground; and a voltage divider, coupled between the second terminal and the third terminal, used to generate a feedback voltage for the voltage sensing input end; wherein the voltage at the second terminal is regulated according to the threshold voltage. | 02-10-2011 |
20110050308 | STANDBY POWER REDUCTION METHOD AND APPARATUS FOR SWITCHING POWER APPLICATIONS - The present invention discloses a standby power reduction method and apparatus for switching power applications, the method comprising the steps of: performing a hysteresis comparison on a supply voltage to generate a selecting signal having a first state and a second state, wherein the hysteresis comparison has a high threshold voltage compared to the supply voltage when the selecting signal is at the first state, and the hysteresis comparison has a low threshold voltage compared to the supply voltage when the selecting signal is at the second state; and determining a UVLO_ON voltage according to the selecting signal, wherein the UVLO_ON voltage is equal to a first level when the selecting signal is at the first state, and the UVLO_ON voltage is equal to a second level when the selecting signal is at the second state. | 03-03-2011 |
20110062886 | OPEN LOOP LED DRIVING CIRCUIT - The present invention discloses an open loop LED driving circuit, having a turn-on period and a turn-off period, the circuit comprising: a power stage, used to store a magnetic energy supplied from a voltage source during the turn-on period and deliver the magnetic energy to a set of LEDs during the turn-off period; and a control unit, having a turn-off period control terminal coupled to the voltage source, and a channel of which a first terminal is coupled to the power stage and a second terminal is coupled to a reference ground, wherein the channel is switched on at a time according to the voltage of the voltage source to determine the turn-off period. | 03-17-2011 |
Kung-Hong Lee, Hsin-Chu City TW
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20080252362 | NEGATIVE VOLTAGE CONVERTER - A negative voltage converter includes six transistors. A first end and a control end of a first transistor are coupled to a signal input. A first end of a second transistor is coupled to the signal input, and a control end of which is coupled to a first clock and the first transistor. A first end of a third transistor is coupled to the signal input, a control end of the third transistor is coupled with a second clock and the second transistor. A first end of a fourth transistor is coupled to the second end of the third transistor, a control end of which is coupled with the first clock and the third transistor. A first end of a fifth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the second clock and the fourth transistor A first end of a sixth transistor is coupled to the second end of the third transistor, and a control end of which is coupled with the first clock and the fifth transistor. | 10-16-2008 |
Ming-Yi Lee, Hsin-Chu City TW
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20150069585 | SEMICONDUCTOR DEVICE WITH AN ANGLED PASSIVATION LAYER - A semiconductor device includes a first passivation layer including a first passivation portion and a second passivation portion substantially diametrically opposite the first passivation portion. The semiconductor device includes a first corner of the first passivation portion separated a first distance from a second corner of the second passivation portion. A third corner of the first passivation portion is separated a second distance from a fourth corner of the second passivation portion. The first distance is not equal to the second distance | 03-12-2015 |
Tung-Hsing Lee, Hsin-Chu City TW
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20080197351 | TESTKEY DESIGN PATTERN FOR GATE OXIDE - A testkey design pattern includes a least one conductive contact, at least one conductive line of a first width vertically and electrically connected to the conductive contact, and at least one pair of source and drain respectively directly connected to each side of the conductive line. The pair of source and drain and part of the conductive line of a first length directly connected to the source and drain form an electronic device. The testkey design patterns are advantageous in measuring capacitance with less error and for better gate oxide thickness extraction. | 08-21-2008 |
Wei-Hua Lee, Hsin-Chu City TW
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20080280382 | Wafer-level test module for testing image sensor chips, the related test method and fabrication - A wafer-level test module is disclosed to include a base layer having multiple first apertures spaced from one another at a pitch corresponding to the pitch of the image sensor chips of an integrated circuit wafer, a cover layer having second apertures respectively axially aimed at the first apertures, and an optical layer sandwiched between the base layer and the cover layer having multiple optical lenses of which the optical axes pass through the first apertures and the second apertures, so that when one image capturing device of the image sensor chips of an integrated circuit wafer is adjusted to the image plane of one of the optical lenses and the wafer-level test module is set in alignment with the integrated circuit wafer horizontally and vertically, then the effective test light can be simultaneously projected onto the image capturing devices of the respective image sensor chips through the wafer-level test module to achieve an effective wafer-level test on multiple image sensor chips of the integrated circuit wafer accurately and rapidly. | 11-13-2008 |
Wen-Fang Lee, Hsin-Chu City TW
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20080299729 | METHOD OF FABRICATING HIGH VOLTAGE MOS TRANSISTOR DEVICE - A substrate is provided, and a sacrificial pattern having an opening partially exposing a high voltage device region is formed on the substrate. Subsequently, a gate oxide layer is formed in the opening, and the sacrificial pattern is removed. A gate electrode, and two heavily doped regions are formed. Than, a salicidation process is carried out to form salicides on the surface of the gate electrode and the heavily doped regions. | 12-04-2008 |
20120313175 | SEMICONDUCTOR DEVICE - The present invention provides a semiconductor device including a substrate, a deep well, a high-voltage well, and a doped region. The substrate and the high-voltage well have a first conductive type, and the deep well and the doped region have a second conductive type different from the first conductive type. The substrate has a high-voltage region and a low-voltage region, and the deep well is disposed in the substrate in the high-voltage region. The high-voltage well is disposed in the substrate between the high-voltage region and the low-voltage region, and the doped region is disposed in the high-voltage well. The doped region and the high-voltage well are electrically connected to a ground. | 12-13-2012 |
20120319189 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE - The present invention provides a high-voltage semiconductor device including a deep well, a first doped region disposed in the deep well, a high-voltage well, a second doped region disposed in the high-voltage well, a first gate structure disposed on the high-voltage well between the second doped region and the first doped region, a doped channel region disposed in the high-voltage region and in contact with the second doped region and the deep well, and a third doped region disposed in the high-voltage well. The high-voltage well has a first conductive type, and the deep well, the first doped region, the second doped region, the doped channel region, and the third doped region have a second conductive type different from the first conductive type. | 12-20-2012 |
Yi-Fang Lee, Hsin-Chu City TW
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20130320191 | OPTICAL DETECTING APPARATUS - An optical detecting apparatus, which comprises: a detecting surface; a first light source, for providing light parallel to the detecting surface; an image sensor, for detecting an object close to the detecting surface, to generate object image data; and an object location determining apparatus, for computing location information of the object according to the object image. | 12-05-2013 |
20140160017 | ELECTRONIC APPARATUS CONTROLL METHOD FOR PERFORMING PREDETERMINED ACTION BASED ON OBJECT DISPLACEMENT AND RELATED APPARATUS THEREOF - An electronic apparatus controlling method includes: determining if displacement of an object in a first predetermined time period is smaller than a first predetermined distance to generate a determining result; and controlling the electronic apparatus to perform a first predetermined action if the determining result is no, and controlling the electronic apparatus to perform a deciding step if the determining result is yes. The deciding step is utilized for deciding if a second predetermined action is performed according to a coordinates of the object at the end of the first predetermined time period. | 06-12-2014 |
20140164756 | CONTROLLING METHOD AND ELECTRONIC APPARATUS UTILIZING THE CONTROLLING METHOD - A controlling method for an electronic apparatus is disclosed. The method comprises: detecting a location for vision of an eye on a display of the electronic apparatus; controlling the electronic apparatus to operate in a first mode if a time period for the vision stops on an objective on the display is not larger than a predetermined time period; and controlling the electronic apparatus to operate in a second mode if the time period for the vision stops on an objective on the display is larger than the predetermined time period. The electronic apparatus detects at least turning operation for a head comprising the eye and performs corresponding operation according to the turning operation in the second mode. | 06-12-2014 |
Yin-Hui Lee, Hsin-Chu City TW
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20130128698 | Object Outline Measuring System - A plurality of sensors are utilized for continuously detecting a plurality of relative distances between a surface of an object and the plurality of sensors within a predetermined space, and are utilized for generating a plurality of distance data according to the plurality of relative distances. A data processing module is utilized for establishing an object outline model of the object according to the plurality of distance data. Therefore, resolution or accuracy of the object outline model generated by measuring an outline of the object can be significantly increased. | 05-23-2013 |
20140098054 | TOUCH MOUSE SUPPORTING KEY FUNCTIONS OF KEYBOARD DEVICE AND RELATED METHOD USED IN TOUCH MOUSE - A method used in a touch mouse includes: providing a touch area; using the touch area to detect a touch of a user's finger on the touch area to sense and generate a touch signal; and, generating a corresponding key output signal to a host by simulating a condition of pressing at least a key of a keyboard device according to the touch signal. | 04-10-2014 |