# Langhammer

## Christoph Langhammer, Mölndal SE

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20100139420 | CELL FOR CONFINEMENT OF VERY SMALL VOLUMES OF SOFT MATTER AND FLUIDS - The present invention relates to a nanocell, and method for manufacturing same, for holding small volumes of soft matter confined in a gap of order 1 micrometer or smaller and measurement systems using the same. The nanocell comprise: | 06-10-2010 |

## Christoph Langhammer, Mölndal SE

Patent application number | Description | Published |
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20100139420 | CELL FOR CONFINEMENT OF VERY SMALL VOLUMES OF SOFT MATTER AND FLUIDS - The present invention relates to a nanocell, and method for manufacturing same, for holding small volumes of soft matter confined in a gap of order 1 micrometer or smaller and measurement systems using the same. The nanocell comprise: | 06-10-2010 |

## Christopher Langhammer, Piscataway, NJ US

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20120004716 | MICROELECTORODE ARRAY, METHODS FOR PREPARING THE SAME AND USES THEREOF - A microelectrode array having a substrate with a plurality of grooves and a plurality of electrical contact pads, the grooves each with at least one electrode electrically connected to at least one of the electrical contact pads, each of the grooves containing at least one myotube that overlays the at least one electrode. | 01-05-2012 |

## Elisa Langhammer, Berlin DE

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20160053379 | ELECTROLESS COPPER PLATING SOLUTION - The invention relates to an electroless aqueous copper plating solution, comprising—a source of copper ions, —a reducing agent or a source of a reducing agent, and—a combination of i) at least one polyamino disuccinic acid, or at least one polyamino monosuccinic acid, or a mixture of at least one polyamino disuccinic acid and at least one polyamino monosuccinic acid, and ii) one or more of a compound which is selected from the group consisting of ethylenediamine tetraacetic acid, N′-(2-Hydroxyethyl)-ethylenediamine-N,N,N′-triacetic acid, and N,N,N′,N′-Tetrakis(2-hydroxypropyl)ethylenediamine, as complexing agents, as well as to a method for electroless copper plating utilizing said solution and the use of the solution for the plating of substrates. | 02-25-2016 |

## Martin Langhammer, Salisbury Wiltshire GB

Patent application number | Description | Published |
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20150088948 | HYBRID ARCHITECTURE FOR SIGNAL PROCESSING - Systems and methods of configuring a programmable integrated circuit. An array of signal processing accelerators (SPAs) is included in the programmable integrated circuit. The array of SPAs is separate from a field programmable gate array (FPGA), and the array of SPAs is configured to receive input data from the FPGA and is programmable to perform at least a filtering function on the input data to obtain output data. | 03-26-2015 |

## Martin Langhammer, Salisbury GB

Patent application number | Description | Published |
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20100228806 | MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY - Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters. | 09-09-2010 |

20110238718 | LOOK UP TABLE STRUCTURE SUPPORTING QUATERNARY ADDERS - A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary (4-1) adder. In some examples, only an XOR gate, an AND gate, two single bit 2-1 multiplexers, and minor connectivity changes to a LUT structure supporting a ternary (3-1) adder are needed to support 4-1 adders. Binary (2-1) and ternary adders are still supported using the original signal flows, as the ternary adder feature can be easily multiplexed out. | 09-29-2011 |

20130311534 | DEVICE WITH LOGIC CIRCUITRY SUPPORTING QUATERNARY ADDITION - A lookup table structure having multiple lookup tables is configured to include a quaternary adder. In particular examples, an adaptive logic module (ALM) including a fracturable lookup table (LUT) is configured to include a quaternary ( | 11-21-2013 |

20140359297 | Systems and Methods for Intermediate Message Authentication in a Switched-Path Network - Systems, methods, and devices are provided for intermediate authentication of a message transmitted through a switched-path network, such as an optical transport network (OTN). In one method, a message transmitted through communication nodes of a switched-path network may be authenticated, at least partially, by authentication logic of one or more of the communication nodes. The one or more communication nodes may identify whether a prior communication node has tampered with or corrupted the message or may generate an authentication tag to enable an authentication authority to authenticate the message. | 12-04-2014 |

## Martin Langhammer, Alderbury GB

Patent application number | Description | Published |
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20090100122 | SATURATION AND ROUNDING IN MULTIPLY-ACCUMULATE BLOCKS - Saturation and rounding capabilities are implemented in MAC blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention. | 04-16-2009 |

20100228807 | Digital signal processing circuitry with redundancy and bidirectional data paths - Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). | 09-09-2010 |

20110161389 | LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE - A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. | 06-30-2011 |

20110219052 | DISCRETE FOURIER TRANSFORM IN AN INTEGRATED CIRCUIT DEVICE - Circuitry performing Discrete Fourier Transforms. The circuitry can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device. The circuitry includes a floating-point addition stage for adding mantissas of input values of the Discrete Fourier Transform operation, and a fixed-point stage for multiplying outputs of the floating-point addition stage by twiddle factors. The fixed-point stage includes memory for storing a plurality of sets of twiddle factors, each of those sets including copies of a respective twiddle factor shifted by different amounts, and circuitry for determining a difference between exponents of the outputs of the floating-point stage, and for using that difference as an index to select from among those copies of that respective twiddle factor in each of the sets. | 09-08-2011 |

20110238720 | SOLVING LINEAR MATRICES IN AN INTEGRATED CIRCUIT DEVICE - Circuitry for solving linear matrix equations involving a resultant matrix, an unknown matrix and a product matrix that is a product of the resultant matrix and the unknown matrix includes matrix decomposition circuitry for triangulating an input matrix to create a resultant matrix having a plurality of resultant matrix elements on a diagonal, and having a further plurality of resultant matrix elements arranged in columns below the resultant matrix elements on the diagonal. The matrix decomposition circuitry includes an inverse square root multiplication path that computes diagonal elements of the resultant matrix having an inverse square root module, and the said inverse square root module computes inverses of the diagonal elements to be used in multiplication in place of division by a diagonal element. Latency is hidden by operating on each nth row of a plurality of matrices prior to any (n+1)th row. | 09-29-2011 |

20110320513 | CALCULATION OF TRIGONOMETRIC FUNCTIONS IN AN INTEGRATED CIRCUIT DEVICE - Circuitry for computing a trigonometric function of an input includes circuitry for relating the input to another value to generate an intermediate value, circuitry for selecting one of the input and the intermediate value as a trigonometric input value, circuitry for determining respective initial values of a plurality of trigonometric functions for the trigonometric input value, and circuitry for deriving, based at least in part on a trigonometric identity, a final value of the first trigonometric function from the respective initial values of the plurality of trigonometric functions. The trigonometric function may be any of sine, cosine and tangent and their inverse functions. The trigonometric identities used allow a computation of a trigonometric function to be broken into pieces that either are easier to perform or can be performed more accurately. | 12-29-2011 |

20120233230 | DOUBLE-CLOCKED SPECIALIZED PROCESSING BLOCK IN AN INTEGRATED CIRCUIT DEVICE - Circuitry for increasing the precision of multipliers by a desired factor while limiting the increase in arithmetic complexity of the multiplier to that factor can be provided in a fixed logic device, or can be configured into a programmable integrated circuit device such as a programmable logic device (PLD). The smaller increase in arithmetic complexity, so that the increase is proportional to the increase in precision, rather than to the square of the increase in precision, is achieved by using specialized processing block components differently on alternating clock cycles. For example, to implement double precision, the same multiplier components are used in each of two clock cycles, but some specialized processing block internal structures (e.g., shifters and adders) are used differently in the two cycles, so that over the two cycles, a larger multiplication may be calculated from smaller partial products. | 09-13-2012 |

20120290819 | DSP BLOCK WITH EMBEDDED FLOATING POINT STRUCTURES - A specialized processing block includes a first floating-point arithmetic operator stage, a second floating-point arithmetic operator stage, and configurable interconnect within the specialized processing block for routing signals into and out of each of the first and second floating-point arithmetic operator stages. In some embodiments, the configurable interconnect may be configurable to route a plurality of block inputs to inputs of the first floating-point arithmetic operator stage, at least one of the block inputs to an input of the second floating-point arithmetic operator stage, output of the first floating-point arithmetic operator stage to an input of the second floating-point arithmetic operator stage, at least one of the block inputs to a direct-connect output to another such block, output of the first floating-point arithmetic operator stage to the direct-connect output, and a direct-connect input from another such block to an input of the second floating-point arithmetic operator stage. | 11-15-2012 |

20130332497 | MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY - Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters. | 12-12-2013 |

20140082035 | MODULAR DIGITAL SIGNAL PROCESSING CIRCUITRY WITH OPTIONALLY USABLE, DEDICATED CONNECTIONS BETWEEN MODULES OF THE CIRCUITRY - Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters. | 03-20-2014 |

20140289293 | LARGE MULTIPLIER FOR PROGRAMMABLE LOGIC DEVICE - A plurality of specialized processing blocks in a programmable logic device, including multipliers and circuitry for adding results of those multipliers, can be configured as a larger multiplier by adding to the specialized processing blocks selectable circuitry for shifting multiplier results before adding. In one embodiment, this allows all but the final addition to take place in specialized processing blocks, with the final addition occurring in programmable logic. In another embodiment, additional compression and adding circuitry allows even the final addition to occur in the specialized processing blocks. | 09-25-2014 |

20150347338 | ACCELERATOR ARCHITECTURE ON A PROGRAMMABLE PLATFORM - An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor. | 12-03-2015 |

## Martin Langhammer, Southway Alderbury GB

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20100169404 | FLEXIBLE ACCUMULATOR IN DIGITAL SIGNAL PROCESSING CIRCUITRY - A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit. | 07-01-2010 |

## Martin Langhammer, Sandbanks GB

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20100007379 | PROGRAMMABLE LOGIC DEVICES WITH FUNCTION-SPECIFIC BLOCKS - A programmable logic integrated circuit device has at least one function-specific circuit block (e.g., a parallel multiplier, a parallel barrel shifter, a parallel arithmetic logic unit, etc.) in addition to the usual multiple regions of programmable logic and the usual programmable interconnection circuit resources. To reduce the impact of use of the function-specific block (“FSB”) on the general purpose interconnection resources of the device, inputs and/or outputs of the FSB may be coupled relatively directly to a subset of the logic regions. In addition to conserving general purpose interconnect, resources of the logic regions to which the FSB are connected can be used by the FSB to reduce the amount of circuitry that must be dedicated to the FSB. If the FSB is a multiplier, additional features include facilitating accumulation of successive multiplier outputs (using either addition or subtraction and with sign extension if desired) and/or arithmetically combining the outputs of multiple multipliers. | 01-14-2010 |

## Nils Langhammer, Verl DE

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20160066759 | METHOD FOR OPERATING A DOMESTIC APPLIANCE SYSTEM - A method for operating a system of at least one stationary domestic appliance and a mobile domestic appliance includes connecting the mobile domestic appliance using wireless communication to the at least one stationary domestic appliance and exchanging data between the mobile domestic appliance and the at least one stationary domestic appliance. | 03-10-2016 |