Patent application number | Description | Published |
20080259668 | Layout structure of bit line sense amplifiers for a semiconductor memory device - A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier. | 10-23-2008 |
20080298111 | Semiconductor memory device - A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line. | 12-04-2008 |
20100085387 | DISPLAY APPARATUS AND TIMING CONTROLLER FOR CALIBRATING GRAYSCALE DATA AND METHOD FOR DRIVING PANEL THEREOF - A display apparatus for calibrating a grayscale data including a timing controller, and a method for driving a panel are provided. A display apparatus includes a timing controller which calibrates the grayscale data of the current frame using the grayscale data of the previous and the current frame and a driving unit which drives a panel using the calibrated grayscale data of the current frame. By generating calibrated grayscale data which are variable according to the change of grayscale, response times of liquid crystal may be improved. | 04-08-2010 |
20100109753 | METHOD OF OUTPUTTING TEMPERATURE DATA IN SEMICONDUCTOR DEVICE AND TEMPERATURE DATA OUTPUT CIRCUIT THEREFOR - A method of outputting temperature data in a semiconductor device and a temperature data output circuit are provided. A pulse signal is generated in response to a booting enable signal activated in response to a power-up signal and the generation is inactivated in response to a mode setting signal during a power-up operation. A comparison signal is generated in response to the pulse signal by comparing a reference voltage independent of temperature with a sense voltage that varies with temperature change. The temperature data is changed in response to the comparison signal. Thus, the temperature data output circuit can rapidly output the exact temperature of the semiconductor device measured during the power-up operation. | 05-06-2010 |
20110103166 | LAYOUT STRUCTURE OF BIT LINE SENSE AMPLIFIERS FOR A SEMICONDUCTOR MEMORY DEVICE - A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier. | 05-05-2011 |
20130329489 | MAGNETO-RESISTIVE MEMORY DEVICE INCLUDING SOURCE LINE VOLTAGE GENERATOR - A MRAM includes a memory cell array of spin-transfer torque magnetic random access memory (STT-MRAM) cells and a source line commonly connected to the plurality of STT-MRAM cells. A source line voltage generator generates a source line driving voltage in response to an external power supply voltage and provides the source line driving voltage to the source line. | 12-12-2013 |