Patent application number | Description | Published |
20110132347 | PORTABLE CHARCOAL GRILL - A portable charcoal grill is disclosed which places charcoal on an internal support mesh located at the bottom of the housing thereof. The portable charcoal grill includes: a fixing string ( | 06-09-2011 |
20130058139 | ENERGY GENERATION SYSTEM AND ITS ANTI ISLANDING PROTECTING METHOD - A new and renewable energy generation system includes: an inverter for converting a DC voltage into an AC voltage; a three-phase/two-phase transformer for transforming an output of the inverter into a three-phase/two-phase stationary coordinate system; a phase locked loop for calculating the phase and frequency of an output voltage of the inverter; a phase shifter for generating a current phase reference value; a current reference coordinate transformer for transforming the current phase reference value and the current amplitude reference value into a two-phase stationary coordinate system; a current phase calculator for outputting a current phase calculation value; a current phase calculator for outputting a current amplitude calculation value; a current adjuster for generating a current adjustment signal; an output three-phase transformer for transforming the current adjustment signal into a current adjustment signal in a three-phase stationary coordinate system; and a PWM controller for outputting a PWM control signal. | 03-07-2013 |
20130076151 | PHOTOVOLTAIC GENERATION SYSTEM USING PARALLEL INVERTER CONNECTED GRID - A photovoltaic generation system using grid-connected parallel inverters comprises a plurality of photovoltaic generation devices connected in parallel with each other, and a transformer configured to transform and transfer output voltages of the photovoltaic generation devices to a grid, wherein the photovoltaic generation device includes: a photovoltaic module configured to convert photovoltaic energy into DC electrical energy; an inverter configured to convert the DC electrical energy outputted from the photovoltaic module into AC electrical energy; an LC filter configured to remove noise included in the AC electrical energy which is outputted from the inverter; and a Y-connected capacitor group which is connected between one terminal of a reactor in the LC filter and one terminal of the photovoltaic module and is configured to reduce stray current. | 03-28-2013 |
20130077366 | SOLAR ENERGY GENERATION SYSTEM TRACKING ADAPTIVE MAXIMUM POWER POINT AND ITS METHOD - Provided are a solar energy generation system having an adaptive maximum power point tracking function and a method thereof. The solar energy generation system includes: a minimum maintenance voltage determination unit configured to output a minimum maintenance voltage which enables the inverter to maintain an operation thereof corresponding to a grid voltage of the grid; a maximum power point tracking controller configured to determine a maximum power point tracking voltage at a maximum power point of the photovoltaic module, using the minimum maintenance voltage and an output voltage and output current of the photovoltaic module, and to output a reference voltage to track the maximum power point; a voltage calculator configured to calculate a difference between the reference voltage and the output voltage of the photovoltaic module; and a voltage adjuster configured to generate a reference current value using an output of the voltage calculator. | 03-28-2013 |
20140254067 | TANTALUM CAPACITOR - Disclosed herein is a tantalum capacitor capable of improving equivalent series resistance (ESR) characteristic by increasing the bond between a tantalum wire and a tantalum powder. The tantalum capacitor according to the present invention includes: a tantalum wire; a tantalum powder having embedded a front end of the tantalum wire and then being sintered; and a rough part formed on a surface of the tantalum wire so as to strengthen a bond between the tantalum wire and the tantalum powder. | 09-11-2014 |
Patent application number | Description | Published |
20090175114 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR - A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports. | 07-09-2009 |
20100232249 | MULTI-PORT SEMICONDUCTOR MEMORY DEVICE HAVING VARIABLE ACCESS PATHS AND METHOD THEREFOR - A multi-port semiconductor memory device having variable access paths and a method therefor are provided. The semiconductor memory device includes a plurality of input/output ports; a memory array divided into a plurality of memory areas; and a select control unit to variably control access paths between the memory areas and the input/output ports so that each memory area is accessed through at least one of the input/output ports. | 09-16-2010 |
20110026335 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal. | 02-03-2011 |
20120026806 | DATA INPUT CIRCUIT - A data input circuit includes a valid strobe signal generation circuit and a data strobe signal counter. The valid strobe signal generation circuit is configured to remove a pulse of an internal strobe signal generated and generate a valid strobe signal. The pulse may have been generated during a preamble period. The data strobe signal counter is configured to count the valid strobe signal according to burst length information and generate a write latch signal for aligning data at a time of a write operation. | 02-02-2012 |
20120113728 | DATA INPUT CIRCUIT - A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal. | 05-10-2012 |
20130127498 | POWER-UP SIGNAL GENERATION CIRCUIT - A power-up signal generation circuit includes a fixed level transition voltage generation unit, a variable level transition voltage generation unit, a comparison unit, and a selective output unit. The fixed level transition voltage generation unit is configured to generate a fixed level transition voltage changing at a constant level of an external voltage. The variable level transition voltage generation unit is configured to generate a variable level transition voltage changing at a level of an external voltage which varies depending on temperature. The comparison unit is configured to compare the level of the fixed level transition voltage with the level of the variable level transition voltage, and generate a selection signal. The selective output unit is configured to output the fixed level transition voltage or the variable level transition voltage as a power-up signal in response to the selection signal. | 05-23-2013 |
20150016196 | DATA INPUT CIRCUIT - A data input circuit includes a clock sampling unit, a final clock generation unit, and a write latch signal generation unit. The sampling unit is configured to generate a shifting signal including a pulse generated after a write latency is elapsed, and generate a sampling clock by sampling an internal clock during a burst period from substantially a time when the pulse of the shifting signal is generated. The final clock generation unit is configured to generate a level signal by latching the shifting signal in synchronization with the sampling clock and generate a final clock from the level signal in response to a burst signal. The write latch signal generation unit is configured to generate an enable signal by latching the final clock and generate a write latch signal for latching and outputting aligned data in response to the enable signal. | 01-15-2015 |
Patent application number | Description | Published |
20080225595 | CHARGE TRAP TYPE NON-VOLATILE MEMORY DEVICE AND PROGRAM METHOD THEREOF - A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell. | 09-18-2008 |
20080230830 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 09-25-2008 |
20090296476 | Flash Memory Device and Method for Manufacturing the Same - A flash memory device includes a substrate, a cell stack having a semiconductor layer, in which junction areas for setting areas therebetween to channel areas are formed in a shape of a stripe, and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked. The flash memory device further includes an array of gate columns penetrating through the cell stack, perpendicular to the substrate and cutting through the junction areas to dispose the junction areas at both sides thereof, and a trap layered stack introduced into an interface between the gate column and the cell stack to store charge. | 12-03-2009 |
20100190315 | METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - There is provided a method of manufacturing a semiconductor memory device. According to the method, a tunnel insulating layer and a charge trap layer are formed in a cell region of a semiconductor substrate defining the cell region and a peripheral region. A gate insulation layer and a first conductive layer are formed over the semiconductor substrate of the peripheral region. A blocking insulating layer is formed on the charge trap layer of the cell region and the first conductive layer of the peripheral region. A second conductive layer is formed over the entire surface including the blocking insulating layer, thereby forming a capacitor having a stack structure of the first conductive layer, the blocking insulating layer, and the second conductive layer. | 07-29-2010 |
20100308398 | Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack - A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge. | 12-09-2010 |
20110204430 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer. | 08-25-2011 |
20120217572 | Flash Memory Device With an Array of Gate Columns Penetrating Through a Cell Stack - A flash memory device includes a substrate; a cell stack having a semiconductor layer for providing junction areas and channel areas and an interlayer isolation layer for insulating the semiconductor layer, wherein the semiconductor layer and the interlayer isolation layer are repeatedly stacked; an array of gate columns, the gate columns penetrating through the cell stack, perpendicular to the substrate; and a trap layered stack introduced into an interface between the gate columns and the cell stack to store charge. | 08-30-2012 |
20130064029 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - An operating method of a semiconductor memory device includes precharging a channel region of a program-inhibited cell of first memory cells coupled to a first word line, selected from a first one of word line groups between a drain select line and a source select line, to a first level based on first data; performing a first program operation for storing the first data in the first memory cells; precharging the channel region of a program-inhibited cell of second memory cells coupled to a second word line, selected from a second one of the word line groups, to a second level based on second data to be stored in the second memory cells; and performing a second program operation for storing the second data in the second memory cells. | 03-14-2013 |
Patent application number | Description | Published |
20090110975 | HYDROGEN GENERATOR AND FUEL CELL USING THE SAME - A hydrogen generator and a fuel cell using the same includes: a first container containing an aqueous solution of alkaline metal carbonate or bicarbonate; a second container containing a metal hydride; and a supply unit disposed between the first container and the second container. The hydrogen generator has a high hydrogen generating rate, can provide a fuel cell with a high energy density, and the amount of hydrogen generated thereby is easy to control. | 04-30-2009 |
20090169966 | FUEL DIFFUSION UNIT, FUEL SUPPLY UNIT, AND FUEL CELL SYSTEM INCLUDING THE SAME - A fuel diffusion unit including: a fuel diffusion plate; a diffusion sheet disposed on fuel diffusion plate, to evenly distribute a fuel to the fuel diffusion plate; a primary transportation unit disposed on the diffusion sheet; secondary transportation units connected to the primary transportation unit, to distribute the fuel to the fuel from the primary transportation unit to the diffusion sheet. The diffusion sheet has a wetting direction that allows the fuel to flow in a predetermined direction. The fuel diffusion unit can be included in a fuel supply unit and a fuel cell system. | 07-02-2009 |
20090176140 | FUEL CELL PROVIDING IMPROVED DISPOSING STRUCTURE FOR UNIT CELLS - A fuel cell including a plurality of unit cells that each includes an anode, an electrolyte membrane, and a cathode. The unit cells are stacked together, such that the unit cells form rows and furrows. The fuel cell can further include an anode frame to support an anode side of the fuel cell stack, and a cathode frame to support a cathode side of the fuel cell stack. The fuel cell can include reinforcing members to support either of the frames. | 07-09-2009 |
Patent application number | Description | Published |
20130236813 | INORGANIC ION CONDUCTOR, METHOD OF FORMING THE SAME, AND FUEL CELL INCLUDING THE INORGANIC ION CONDUCTOR - An inorganic ion conductor including a trivalent metallic element, a pentavalent metallic element, phosphorus, and oxygen. | 09-12-2013 |
20140099563 | FUEL CELL STACK HAVING COOLING MEDIUM LEAKAGE PREVENTING UNIT - A fuel cell stack includes a plurality of unit cells, a cooling plate and a block plate. Each unit cell includes a cathode electrode and an anode electrode respectively at opposing sides of an electrolyte membrane, and a separator facing each of the cathode electrode and the anode electrode. The cooling plate is between adjacent unit cells a cooling medium flows in the cooling plate. The block plate is between the cooling plate and an adjacent unit cell of the adjacent unit cells. The block plate blocks the cooling medium flowing in the cooling plate from contacting the adjacent unit cell of the adjacent unit cells. | 04-10-2014 |
20140134519 | ELECTROLYTE MEMBRANE FOR FUEL CELL, ELECTRODE FOR FUEL CELL, AND FUEL CELL EMPLOYING THE SAME - An electrolyte membrane for a fuel cell includes: an inorganic ionic conductor including a trivalent metal element, a pentavalent metal element, phosphorous, and oxygen; and a polymer. | 05-15-2014 |
Patent application number | Description | Published |
20110318535 | THREE-DIMENSIONAL NANOSTRUCTURES AND METHOD FOR FABRICATING THE SAME - A three-dimensional nanostructures and a method for fabricating the same, and more particularly to three-dimensional structures of various shapes having high aspect ratio and uniformity in large area and a method of fabricating the same by attaching a target material to the outer surface of patterned polymer structures using an ion bombardment phenomenon occurring during a physical ion etching process to form target material-polymer composite structures, and then removing the polymer from the target material-polymer structures. A three-dimensional nanostructures with high aspect ratio and uniformity can be fabricated by a simple process at low cost by using the ion bombardment phenomenon occurring during physical ion etching. Also, nanostructures of various shapes can be easily fabricated by controlling the pattern and shape of polymer structures. In addition, uniform fine nanostructures having a thickness of 10 nm or less can be formed in a large area. | 12-29-2011 |
20120000556 | Drive-Integrated Type BLDC Fuel Pump Module - Provided is a driver-integrated type BLDC fuel pump module, which is used in a vehicle and in which a driver used for controlling the operation of a BLDC fuel pump is installed in a flange of the BLDC fuel pump module, thus removing the spatial limit caused when the driver is installed and reducing the length of an electric wire electrically connecting the driver to a BLDC fuel pump of the module, thereby solving the problem of the operational performance of the BLDC fuel pump deteriorating as a result of both the voltage drop in the electric wire and a reduction in the operational efficiency of the pump. | 01-05-2012 |
20150060392 | THREE-DIMENSIONAL NANOSTRUCTURES AND METHOD FOR FABRICATING THE SAME - A three-dimensional nanostructures and a method for fabricating the same, and more particularly to three-dimensional structures of various shapes having high aspect ratio and uniformity in large area and a method of fabricating the same by attaching a target material to the outer surface of patterned polymer structures using an ion bombardment phenomenon occurring during a physical ion etching process to form target material-polymer composite structures, and then removing the polymer from the target material-polymer structures. A three-dimensional nanostructures with high aspect ratio and uniformity can be fabricated by a simple process at low cost by using the ion bombardment phenomenon occurring during physical ion etching. Also, nanostructures of various shapes can be easily fabricated by controlling the pattern and shape of polymer structures. In addition, uniform fine nanostructures having a thickness of 10 nm or less can be formed in a large area. | 03-05-2015 |
Patent application number | Description | Published |
20080293200 | Method of fabricating nonvolatile semiconductor memory device - In a nonvolatile semiconductor memory device, and a method of fabricating the same, the nonvolatile semiconductor memory device includes a cell doping region and source/drain regions in a semiconductor substrate, the cell doping region being doped as a first conductive type, a channel region disposed between the source/drain regions in the semiconductor substrate, a tunnel doping region of the first conductive type formed in a predetermined region of an upper portion of the cell doping region, the tunnel doping region being doped in a higher concentration than that of the cell doping region, a tunnel insulating layer formed on a surface of the semiconductor substrate on the tunnel doping region, a gate insulating layer surrounding the tunnel insulating layer and covering the channel region and the cell doping region exposed beyond the tunnel doping region, and a gate electrode covering the tunnel insulating layer and on the gate insulating layer. | 11-27-2008 |
20100155958 | BONDING PAD STRUCTURE AND MANUFACTURING METHOD THEREOF - A bonding pad structure of a semiconductor device and a method of manufacturing the same reduce the likelihood of peel-off defects from occurring. The bonding pad structure includes a substrate, an interlayer insulation layer on the substrate, an upper wiring layer on the interlayer insulation layer, and a plurality of lower wiring layers disposed in the interlayer insulation layer between the upper wiring layer and the substrate and configured to prevent the interlayer insulation layer from cracking especially during a wire bonding process in which a wire is bonded to the upper wiring layer. For example, the respective areas occupied by the lower wiring layers sequentially increase in the interlayer insulation layer in a downward direction from the upper wiring layer towards the substrate. Also, each of the lower wiring layers may project further inwardly toward a central part of the bonding pad than the lower layer of wiring disposed above it in the interlayer insulation layer. | 06-24-2010 |