Patent application number | Description | Published |
20100199154 | Reduced processing in high-speed Reed-Solomon decoding - Processing polynomials is disclosed. At least a portion of processing associated with an error evaluator polynomial and at least a portion of processing associated with an error locator polynomial are performed simultaneously. The error evaluator polynomial and the error locator polynomial are associated with Berlekamp-Massey processing. Data associated with the error evaluator polynomial is removed, including by shifting data in an array so that at least one element in the array is emptied in a shift. | 08-05-2010 |
20110125959 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND flash memory system is controlled by determining whether to change a value of a voltage threshold. The voltage threshold is associated with an erase operation to a portion of a NAND flash memory chip. In the event it is determined to change the value of the voltage threshold, the value of the voltage threshold is changed and the changed value of the voltage threshold and an identifier associated with the portion of the NAND flash memory chip is stored. | 05-26-2011 |
20110191653 | QUASI-CYCLIC LDPC ENCODING AND DECODING FOR NON-INTEGER MULTIPLES OF CIRCULANT SIZE - In processing quasi-cyclic low-density parity-check (QC-LDPC) data, an input signal is received which includes decision and reliability information corresponding to unpadded data. Decision and reliability information corresponding to padded data is introduced into the input signal. Message passing is performed one or more times to obtain decoded data. This includes using (1) the decision and reliability information corresponding to the unpadded data and (2) the decision and reliability information corresponding to the padded data, where a preference is given to the decision and reliability information corresponding to the padded data over the decision and reliability information corresponding to the padded data during message passing. Zero padding is removed from the decoded data. | 08-04-2011 |
20110239085 | ECC WITH OUT OF ORDER COMPLETION - Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder. | 09-29-2011 |
20110252294 | IMPLEMENTATION OF LDPC SELECTIVE DECODING SCHEDULING - A method for decoding data is disclosed. The method includes partitioning a low-density parity check (LDPC) matrix into a plurality of groups, each comprising one or more check node layers. The method further includes selecting one of the groups based at least in part on a cost function, the cost function based at least in part on information associated with a variable node, or information associated with a check node, or both. The method further includes performing LDPC layered decoding on the selected group. | 10-13-2011 |
20120019950 | PAD BIT INJECTION DURING READ OPERATION TO IMPROVE FORMAT EFFICIENCY - Injecting pad bits during a read operation to improve format efficiency is disclosed. In some embodiments, a pad sequence associated with error correction is not stored in a sector on a disk. Instead, the pad sequence is merged at a read channel with data stored in a sector that is accessed by the read channel. | 01-26-2012 |
20120081971 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits. | 04-05-2012 |
20120099217 | SPLIT SECTOR FORMATTING OF STORAGE DISKS - A length of a separator to be skipped on the storage disk is compared with a threshold. The threshold is associated with a maximum value for which a timing loop is able to be paused without causing the timing loop to have inaccurate timing. If the length is greater than the threshold, a first split sector format is assigned to the split sector and that information is recorded. In such cases, a first portion and a second portion both include synchronization information. If the length is less than the threshold, a second split sector format is assigned to the split sector and that information is recorded. In such cases, the first portion includes synchronization information and the second portion of the split sector excludes synchronization information. | 04-26-2012 |
20120246536 | LDPC SELECTIVE DECODING SCHEDULING USING A COST FUNCTION - A cost function is obtained. For each of a plurality of groups of check nodes associated with low-density parity-check (LDPC) encoded data, the cost function is evaluated using information associated with a variable node and/or information associated with a check node. One of the groups of check nodes is selecting based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of check nodes. | 09-27-2012 |
20120260114 | ON DEMAND HARD DISK DRIVE SYSTEM ON A CHIP POWER CONTROL SCHEME - An access instruction associated with accessing a target location in a disk is obtained. A number of units until the target location is accessed is calculated. It is determined whether there is time for the group of logic to transition from a lower power state to an operational state; the determination is based at least in part on the number of units between a current location of a read head associated with the hard disk system and the target location which is different from the current location of the read head and a warm up time associated with the group of logic. If it is determined there is time, the group of logic is put into the lower power state. | 10-11-2012 |
20130086446 | SOVA SHARING DURING LDPC GLOBAL ITERATION - Decoding is performed on input data to obtain first decoded data using a first error correction decoder. If decoding by a second error correction decoder on the first decoded data fails, decoding is performed using an output of the second decoder and using the first decoder. A reservation request is sent from the second error correction decoder to a memory prior to completion of the decoding on the first decoded data. Space is reserved in the memory in response to receiving the reservation request from the second decoder. | 04-04-2013 |
20130185615 | SOFT OUTPUT VITERBI DETECTOR WITH ERROR EVENT OUTPUT - A first sequence of states associated with a surviving path and a second sequence of states associated with a non-surviving path are determined. A possible error event is determined based at least in part on the first sequence of states and the second sequence of states. The first sequence of states is replaced with the second sequence of states by applying the possible error event to the first sequence of states. | 07-18-2013 |
20130208540 | E/P DURABILITY BY USING A SUB-RANGE OF A FULL PROGRAMMING RANGE - An instruction to perform an erase on a group of one or more memory cells is sent. An indication that the erasure of the group of memory cells is unsuccessful is received. In response to receiving the indication that the erasure of the group of memory cells is unsuccessful, the value of a voltage threshold, associated with the group of memory cells, is changed to a new voltage threshold and the new voltage threshold and identification information associated with the group of memory cells is stored. | 08-15-2013 |
20130246880 | LDPC SELECTIVE DECODING SCHEDULING USING A COST FUNCTION - A cost function is obtained. For each of a plurality of groups of nodes, the cost function is evaluated by obtaining, for a given group of nodes, one or more reliability values associated with the given group of nodes; the one or more reliability values include sign and magnitude. For a given group of nodes, a reliability value with a smallest magnitude is selected where the evaluated cost function for the given group of nodes is set to the smallest magnitude. One of the plurality of groups of nodes is selected based at least in part on the evaluated cost functions. Error correction decoding related processing is performed on the selected group of nodes. | 09-19-2013 |
20140325313 | MEMORY PROTECTION CACHE - Accessing data at a memory is described. A request associated with a read or write operation is received, wherein the request includes a logical address associated with the memory. A physical address is generated based at least in part on the logical address. A block of data at the memory that includes data associated with the physical address is determined. Data at the determined block of data and a corresponding set of ECC from the memory are accessed. Whether the accessed data can be decoded based at least in part on the corresponding set of ECC is determined. | 10-30-2014 |
20140365716 | INTERFACE BETWEEN MULTIPLE CONTROLLERS - A second controller is communicated with from a first controller via an interface. Storage is also communicated with from the first controller via the interface. The first controller is configured to be a master on the interface and the second controller and the storage are configured to be targets on the interface. | 12-11-2014 |
20150033093 | ADVANCE CLOCKING SCHEME FOR ECC IN STORAGE - A system for clocking a decoder is disclosed. The system includes: a channel front end configured to receive input data, a first clock configured to provide a first clock signal as input to the channel front end, a decoder configured to receive intermediate data associated with the output of the channel front end, and a second clock configured to provide a second clock signal as input to the decoder. In some embodiments, the second clock signal is not derived from the first clock signal. | 01-29-2015 |