Patent application number | Description | Published |
20090185438 | SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY CIRCUIT FOR REPAIRING DEFECTIVE UNIT CELL, AND METHOD FOR REPAIRING DEFECTIVE UNIT CELL - A semiconductor memory device includes banks of unit cells, wherein two or more adjacent banks of the banks share a redundancy circuit configured to perform a defect repair operation when an address for accessing a defective unit cell is input. | 07-23-2009 |
20100033221 | CONTROL CIRCUIT OF READ OPERATION FOR SEMICONDUCTOR MEMORY APPARATUS - A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first delay unit that is configured to generate and output a first delay signal to a first global input/output line driver by receiving a sensing-enable signal ‘IOSTB’, and to generate and output a second delay signal to a second global input/output line driver by receiving the sensing-enable signal. The first delay unit generates the second delay signal by delaying the sensing-enable signal in synchronization with a clock. The semiconductor memory apparatus also includes a second delay unit configured to generate a pipe latch control signal in response to the first delay signal and the second delay signal. | 02-11-2010 |
20100118629 | APPARATUS FOR CONTROLLING I/O STROBE SIGNAL IN SEMICONDUCTOR MEMORY APPARATUS - A sensing enable signal control circuit determines a driving timing of an I/O sense amplifier based on a read-out result of data, which is stored in a dummy cell of a semiconductor memory apparatus. The sensing enable signal control circuit in a semiconductor memory apparatus includes a detection code generating unit configured to output a detection code according to a voltage level of dummy cell data, which are read out from a dummy cell through at least one read operation, in response to a column select enable signal, and a multiplexer configured to receive the detection code and a default code and output a delay code to delay a sensing enable signal. | 05-13-2010 |
20100246296 | Write Driver and Semiconductor Memory Device Using the Same - A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a common write control block configured to generate common drive control signals corresponding to write data, and a common write drive block configured to drive transmission lines of a first memory bank or transmission lines of a second memory bank that are selected by a bank selection signal in response to the common drive control signals. | 09-30-2010 |
20110002179 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks. | 01-06-2011 |
20110103163 | MULTI-BIT TEST CONTROL CIRCUIT - A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test. | 05-05-2011 |
20110158012 | SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY CIRCUIT FOR REPAIRING DEFECTIVE UNIT CELL - A semiconductor memory device includes a first bank including a plurality of cell matrices a second bank including a plurality of cell matrices and a shared-fuse set, which is shared by the first and second banks, configured to output a defect indication signal when the first bank or the second bank is enabled and a defective cell matrix is included in the enabled bank. | 06-30-2011 |
20110235452 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device including an information storage unit comprising a fuse configured to store information, a control unit configured to control a node of a blown fuse to become a floating state in response to a control pulse signal, and an output unit configured to output the information. | 09-29-2011 |
20120008441 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device includes a repair control signal generation unit configured to compare a repair target address programmed corresponding to a repair target memory cell with an external address, and generate a repair control signal. an address decoding unit configured to control a normal memory cell or a redundancy memory cell corresponding to the external address to be accessed in response to the repair control signal and an internal active signal, and an activation interval detection unit configured to generate an interval detection signal by detecting a time interval between an activation timing of the repair control signal and an activation timing of the internal active signal in a test operation mode. | 01-12-2012 |
20120033511 | CONTROL CIRCUIT OF READ OPERATION FOR SEMICONDUCTOR MEMORY APPARATUS - A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first line driver configured to output a portion of a output signals from sense amplifier according to a first delay signal; a second line driver configured to output a rest of the output signals from the sense amplifier according to a second delay signal; and a first delay unit configured to output a second delay signal synchronized with a clock to the second line driver. | 02-09-2012 |
20120092947 | FUSE CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME - A fuse circuit includes a plurality of fuse cells, an amplification unit, and a plurality of registers. The amplification unit is configured to sequentially amplify data stored in the fuse cells. The registers are configured to sequentially store data amplified by the amplification unit. | 04-19-2012 |
20120096322 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a memory controller chip, a plurality of first memory chips configured to store normal data, a second memory chip configured to store error information for correcting or detecting error of the normal data, and an interface unit configured to interface the memory controller chip, the plurality of first memory chips, and the second memory chip. | 04-19-2012 |
20130148449 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes first and second write driving blocks to perform a data write operation on first and second memory banks in response to first and second bank strobe signals, respectively, and a common input driving block to transmit data to the first and second write driving blocks through a common data line in response to access information of the first and second memory banks. | 06-13-2013 |
20130162263 | FUSE CIRCUIT AND TESTING METHOD OF THE SAME - A fuse circuit includes a data line, a plurality of fuse cells selectively programmed and electrically connected with the data line in response to respective selection signals, a dummy fuse cell electrically connected with the data line in response to a test signal, and a sense amplifier configured to sense a data of the data line. The fuse circuit includes a plurality of fuses, reduces the area thereof, and easily detects whether a sense amplifier operates properly or not in the fuse circuit. | 06-27-2013 |
20130279272 | SEMICONDUCTOR DEVICE HAVING FUSE CIRCUIT - A semiconductor device includes a pulse generation circuit configured to generate an enable pulse signal, which is activated in response to an active command signal and deactivated in response to a column command signal, and a plurality of fuse circuits configured to store repair addresses for a column repair and to output stored repair addresses in response to the enable pulse signal. | 10-24-2013 |
20130279279 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fuse unit connected to a detection node and configured to be programmed in response to a first voltage supplied through the detection node, an output unit connected to the detection node and configured to output a fuse information signal indicating whether the fuse unit is programmed or not, and a blocking unit configured to block the first voltage supplied through the detection node in response to the fuse information signal. | 10-24-2013 |
20130279282 | E-FUSE ARRAY CIRCUIT - An e-fuse array circuit includes a first select transistor configured to have a gate terminal connected to a first select line and have a first terminal connected to a first bit line, a first e-fuse transistor configured to have a gate terminal connected to a common program/read line and have a first terminal connected to a second terminal of the first select transistor, a second select transistor configured to have a gate terminal connected to a second select line and have a first terminal connected to the first bit line, and a second e-fuse transistor configured to have a gate terminal connected to the common program/read line and have a first terminal connected to a second terminal of the second select transistor. | 10-24-2013 |
20150043288 | SEMICONDUCTOR MEMORY DEVICE HAVING FUSE CELL ARRAY - A semiconductor memory device includes a plurality of fuses arranged in an array suitable for storing N number of repair column addresses, each having M bits and corresponding to a repair target memory cell, a fuse selection unit suitable for selecting M fuses corresponding to one of the N number of repair column addresses in the plurality of fuses in response to an active command and an external row address, which are applied from outside, and outputting one of the N number of repair column addresses corresponding to the selected M fuses, and a repair determination unit suitable for determining whether or not a column address applied from the outside corresponds to the repair target memory cell based on the repair column address outputted by the fuse selection unit. | 02-12-2015 |