Patent application number | Description | Published |
20100008166 | CIRCUIT AND METHOD FOR CONTROLLING LOADING OF WRITE DATA IN SEMICONDUCTOR MEMORY DEVICE - A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing on the global bus in response to a control signal; and a memory bank configured to write the data of the first burst length or the data of the second burst length. | 01-14-2010 |
20100049911 | Circuit and Method for Generating Data Input Buffer Control Signal - A data input buffer control signal generating device is capable of preventing unnecessary operation and current consumption of blocks and thus stabilizing an internal operation of DRAM by generating a control signal which controls an enabling timing of a data input buffer not to be conflicted with an output data. The data input buffer control signal generating device includes a write-related control unit configured to generate a data input buffer reference signal generated on the basis of a write latency by a write command, a read-related control unit configured to replicate a delay through a data output path, delay an end command for a data output termination and generate a delayed end command, wherein the end command is generated by a read command, and an output unit configured to output a data input buffer control signal by combining the data input buffer reference signal and the output of the delayed end command. | 02-25-2010 |
20100308883 | BURST ORDER CONTROL CIRCUIT AND METHOD THEREOF - A burst order control circuit includes a burst signal generating unit configured to receive a seed column address and to generate a first rising burst signal, a second rising burst signal, a first falling burst signal and a second falling burst signal in response to the seed column address, and a repeater unit configured to transfer the first rising burst signal, the second rising burst signal, the first falling burst signal and the second failing burst signal to a pipe latch. | 12-09-2010 |
20110216606 | DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values. | 09-08-2011 |
20120281157 | DISPLAY APPARATUS AND METHOD FOR MANUFACTURING THE SAME - A display apparatus used for creating 3D images has a display panel and a phase-delaying layer disposed on the display panel. The phase-delaying layer has first and second light-changing patterns that are self-aligned to at least one of pixels and a black matrix of the display panel. The self-aligned structure is formed by selectively passing curing light (e.g., UV light) through the display panel to cure curable liquid crystal films while the films are respectively aligned by aligning layers having different alignments. | 11-08-2012 |
20130162316 | PULSE GENERATION CIRCUIT, BURST ORDER CONTROL CIRCUIT, AND DATA OUTPUT CIRCUIT - A pulse generation circuit includes a control unit configured to activate one or more of control clocks among a plurality of control clocks, and to activate one or more of select signals among a plurality of select signals, in response to one or more of sequence signals; a plurality of shifting units each configured to generate one or more of output signals, and to sequentially activate the one or more of output signals by shifting an input pulse when a corresponding control clock among the plurality of control clocks is activated; and a signal transfer unit configured to transfer one or more of output signals of a shifting unit corresponding to an activated select signal among the plurality of shifting units, as one or more of pulses. | 06-27-2013 |
20140016416 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME - Provided is a semiconductor memory device in which a plurality of first and second data lines coupled to a memory cell array are alternately arranged. The semiconductor memory device includes a first write driving circuit configured to load a plurality of first write data transmitted through a plurality of third data lines into the plurality of first data lines in response to a first write enable signal; a second write driving circuit configured to load a plurality of second write data transmitted through a plurality of fourth data lines into the plurality of second data lines in response to a second write enable signal; and a column control circuit configured to activate at least one of the first and second write enable signals during a given period, in response to a plurality of data width option modes, during a parallel test mode. | 01-16-2014 |
20150177777 | PULSE GENERATION CIRCUIT, BURST ORDER CONTROL CIRCUIT, AND DATA OUTPUT CIRCUIT - A pulse generation circuit includes a control unit configured to activate one or more of control clocks among a plurality of control clocks, and to activate one or more of select signals among a plurality of select signals, in response to one or more of sequence signals; a plurality of shifting units each configured to generate one or more of output signals, and to sequentially activate the one or more of output signal's by shifting an input pulse when a corresponding control clock among the plurality of control clocks is activated; and a signal transfer unit configured to transfer one or more of output signals of a shifting unit corresponding to an activated select signal among the plurality of shifting units, as one or more of pulses. | 06-25-2015 |