Kushnick
Eric Kushnick, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20100275072 | CORRECTING APPARATUS, PDF MEASUREMENT APPARATUS, JITTER MEASUREMENT APPARATUS, JITTER SEPARATION APPARATUS, ELECTRIC DEVICE, CORRECTING METHOD, PROGRAM, AND RECORDING MEDIUM - There is provided a correcting apparatus for correcting a PDF obtained from a measurement result of measuring a characteristic of a measurement target at strobe timings including errors with respect to ideal timings at predetermined intervals, the correcting apparatus including: an interpolation section that is supplied with a CDF of the measurement result, interpolates a value between each strobe timing of the CDF, calculates a value of the CDF at each of the ideal timings, and calculates a corrected CDF at the ideal timings; and a corrected function generating section that generates a corrected PDF in which the errors of the strobe timings for the PDF have been corrected, based on the corrected CDF calculated by the interpolation section. | 10-28-2010 |
Eric Kushnick, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20140236525 | TEST ARCHITECTURE HAVING MULTIPLE FPGA BASED HARDWARE ACCELERATOR BLOCKS FOR TESTING MULTIPLE DUTS INDEPENDENTLY - Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components. | 08-21-2014 |
20150028908 | HIGH SPEED TESTER COMMUNICATION INTERFACE BETWEEN TEST SLICE AND TRAYS - A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces. | 01-29-2015 |
Eric B. Kushnick, Alamo, CA US
Patent application number | Description | Published |
---|---|---|
20110234271 | HIGH RESOLUTION CLOCK SIGNAL GENERATOR - A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period T | 09-29-2011 |
Eric Barr Kushnick, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20140070831 | SYSTEM AND METHOD OF PROTECTING PROBES BY USING AN INTELLIGENT CURRENT SENSING SWITCH - An apparatus and method for protecting probes used in automated testing is disclosed. The apparatus comprises a probe operable to provide power to a device under test (DUT) from a device power source (DPS), wherein the probe is coupled to a contact point on the DUT and a probe protector circuit connected to the probe in series between the DPS and the DUT. The probe protector circuit further comprises a current sense module operable to monitor a flow of current from the DPS to the DUT to determine if the current flow is below a predetermined threshold current level and a switch for controlling the connection from the DPS to the DUT. The switch is coupled to the current sense module and is operable to be used in conjunction with the current sense module to limit the current flow if it exceeds the predetermined threshold current level. | 03-13-2014 |
Eric Barr Kushnick, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20090103388 | HISTOGRAM GENERATION WITH BANKS FOR IMPROVED MEMORY ACCESS PERFORMANCE - Dividing memory used for storing histogram data into multiple banks is disclosed to allow for phased RMW cycles. Although the same address lines are provided to each bank, address control logic ensures that each successive RMW cycle is handled by a different bank, so that another RMW cycle can be started in one bank while the previous RMW cycle is still being performed in another bank. By staggering or phasing the starts of the RMW cycles in a wraparound fashion, each histogram bin is spread out over multiple banks, but testing can proceed faster than if only a single bank was used. After the histogram data has been captured, the areas of memory in each bank associated with a particular bin can be added together to compute the total count for that bin. | 04-23-2009 |
20090106512 | HISTOGRAM GENERATION WITH MIXED BINNING MEMORY - Memory is divided up during the gathering of histogram data so that a portion of the memory is configured for storing the high counts expected at the minimum and maximum codes/addresses, and at least one other portion is configured for storing the lower counts expected at other codes/addresses. By configuring memory portions in this manner, memory can be more efficiently allocated. | 04-23-2009 |
20100229053 | METHOD AND APPARATUS FOR TIME VERNIER CALIBRATION - Disclosed is a method and apparatus for calibrating a time vernier with an input data signal, a reference signal and a third trigger signal, all of which have pre-defined related frequencies so as to allow for accurate determination of vernier delays and strobe placement in an ATE system. | 09-09-2010 |
20100278226 | TRANSMISSION CIRCUIT, DIFFERENTIAL SIGNAL TRANSMISSION CIRCUIT, AND TEST APPARATUS - Provided is a test apparatus, a differential signal transmission circuit, and a transmission circuit that transmits signals between an input terminal and an output terminal, comprising a first high frequency signal passing section that blocks a low frequency signal that has a frequency less than a predetermined reference frequency in a signal received from the input terminal, and transmits a high frequency signal that has a frequency greater than or equal to the predetermined reference frequency to the output terminal; an input-side low frequency signal passing section that passes the low frequency signal in the signal from the input terminal and attenuates the high frequency signal; an output-side low frequency signal passing section that transmits to the output terminal the low frequency signal passed by the input-side low frequency signal passing section and attenuates the high frequency signal from the first high frequency signal passing section; and a switching section that switches a connection between the input-side low frequency signal passing section and the output-side low frequency signal passing section. | 11-04-2010 |
Steven Kushnick, Marietta, GA US
Patent application number | Description | Published |
---|---|---|
20120055089 | SYSTEM AND PROCESS FOR GASIFYING BIOMASS PRODUCTS - A system for gasifying biomass materials is provided. The system includes a gasifying unit for converting the biomass materials into a gas and a feeder mechanism for introducing the biomass materials into the gasifying unit. The gasifying unit includes a plurality of gasifying medium and biomass injection ports distributed along a vertical length of the gasifying unit, and each of the plurality of injection ports has a corresponding injection angle. The injection angles include at least one of an upward tangential angle and a downward tangential angle. | 03-08-2012 |
William B. Kushnick, Oak Ridge, NJ US
Patent application number | Description | Published |
---|---|---|
20140110449 | Wire Pulling Device - The current disclosure describes and teaches a wire pulling device having a base member. A vertical post and a horizontal post are attached to the base member, serving as anchoring posts for a clevis that may be opened and closed. The device may be attached to installation sites for wires and cables. Using an attachment mechanism, the base member may be affixed to a joist, a rafter, or an angle iron. Wires or cables may be threaded or disposed into the clevis and suspended to the installation sites. An installer may pull the wire or cable to proper positions before permanent affixations such as wire ties may be applied. The current device and its associated method facilitate the wire installation process. | 04-24-2014 |