Patent application number | Description | Published |
20090059951 | PROGRAM CONTROL DEVICE - Provided is a program control device which switches, per timeslot, between threads to be executed. The program control device includes: a first interrupt creation unit which creates a first interrupt signal which designates a timeslot as a destination; and a first receiving unit which [i] does not receive the first interrupt signal if the timeslot as the destination is not a current timeslot, and [ii] receives the first interrupt signal if the timeslot as the destination is the current timeslot. | 03-05-2009 |
20090083748 | PROGRAM EXECUTION DEVICE - A resource information acquiring unit acquires processor resource information from outside. A program associating unit associates the processor resource information with a program. A processor resource allocating unit allocates processor resources to the program in accordance with the processor resource information when the program is executed. | 03-26-2009 |
20110185363 | TASK SWITCHING APPARATUS, METHOD AND PROGRAM - A method of assigning task management blocks for first type tasks to time slot information on a one-by-one basis, assigning a plurality of task management blocks for second type tasks to time slot information, selecting a task management block according to a priority classification when switching to the time slot of the time slot information, and switching to the time slot except the time slot information. Additionally a task switching apparatus selects the task management block assigned to the time slot and executes the task. | 07-28-2011 |
20120030430 | CACHE CONTROL APPARATUS, AND CACHE CONTROL METHOD - A cache control apparatus according to the present invention includes a cache allocation control unit which allocates each of a plurality of ways included in a cache memory to one or more of tasks to be executed by a plurality of processors. In the case where a group of ways includes an unallocated way that is not allocated to any of the tasks and a way allocated to one or more of the tasks which is to be executed by one of the processors, the cache allocation control unit allocates the unallocated way included in the group to the one or more of the tasks to be executed by the one of the processors. | 02-02-2012 |
20130318544 | PROGRAM GENERATION DEVICE, PROGRAM GENERATION METHOD, PROCESSOR DEVICE, AND MULTIPROCESSOR SYSTEM - A program generation device for generating, from a source program, machine programs corresponding to a plurality of processors having different instruction sets and sharing a memory, the program generation device including: a switch point determination unit for determining a switch point in the source program; a switchable-program generation unit for generating a switchable program for each processor so that a data structure of the memory is commonly shared at a switch point among the plurality of processors; and a switch decision process insertion unit for inserting into the switchable programs a switch program for stopping at the switch point a switchable program being executed by and corresponding to a first processor, and causing a second processor to execute, from the switch point, a switchable program corresponding to the second processor. | 11-28-2013 |
20140196045 | PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION - A processor executes a plurality of tasks by switching a timeslot and iterating a plurality of timeslots. The processor includes a table in which tasks are defined in correspondence with timeslots. In the table, the number of timeslots to be held in one iteration is defined, for each of the timeslots a total time period during the predetermined number of iterations is designated, and a plurality of tasks are defined in correspondence with at least one of the timeslots. A timeslot is switched every time a predetermined period elapses. One task is selected and executed by referring to the table in correspondence with switching of timeslot. | 07-10-2014 |
Patent application number | Description | Published |
20080209162 | PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION - A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group. | 08-28-2008 |
20080209192 | PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION - A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group. | 08-28-2008 |
20080215858 | PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION - A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group. | 09-04-2008 |
20110283288 | PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION - A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group. | 11-17-2011 |
Patent application number | Description | Published |
20120121965 | SECONDARY BATTERY, BATTERY UNIT, AND BATTERY MODULE - There is provided a secondary battery including a battery device that has a thickness of 3 to 20 mm, and a battery discharge capacity of 3 to 50 Ah, and an exterior material that packages the battery device. The battery device includes a positive electrode that has a positive electrode current collector and a positive electrode active material layer, a negative electrode that has a negative electrode current collector and a negative electrode active material layer, a separator that is interposed between the positive electrode and the negative electrode that are alternately laminated, a positive electrode tab that is electrically connected to a positive electrode current collector exposed portion and is led-out to the outside of the exterior material, and a negative electrode tab that is electrically connected to a negative electrode current collector exposed portion and is led-out to the outside of the exterior material. | 05-17-2012 |
20120121967 | Non-Aqueous Electrolyte Battery - A non-aqueous electrolyte battery includes a battery device in which a positive electrode is faced to negative electrode through a separator; a non-aqueous electrolyte; a laminate film which is formed by laminating a metal layer, an outside resin layer formed in outer face of the metal layer, and an inside resin layer formed in the metal layer, and in which the battery device and the non-aqueous electrolyte is packaged by heat welding and housed; a positive electrode lead which is electrically connected to the positive electrode, and drawn from portion heat-welded of the laminate film to an exterior thereof; a negative electrode lead which is electrically connected to the negative electrode, and drawn from portion heat-welded of the laminate film to an exterior thereof; and a porous polymer layer containing, as a component, vinylidene fluoride formed between the laminate film and the battery device. | 05-17-2012 |
20120321911 | NON-AQUEOUS ELECTROLYTE BATTERY, NON-AQUEOUS ELECTROLYTE BATTERY POSITIVE ELECTRODE, NON-AQUEOUS ELECTROLYTE BATTERY NEGATIVE ELECTRODE, NON-AQUEOUS ELECTROLYTE BATTERY SEPARATOR, ELECTROLYTE FOR NON-AQUEOUS ELECTROLYTE, AND METHOD OF MANUFACTURING NON-AQEUOUS ELECTROLYTE BATTERY SEPARATOR - A battery is composed of a positive electrode in which a positive electrode active material layer including a positive electrode active material is formed on a positive electrode collector, a negative electrode in which a negative electrode active material layer including a negative electrode active material is formed on a negative electrode collector, a separator provided between the positive electrode and the negative electrode, and an electrolyte impregnated in the separator. The battery further includes at least one of a heteropoly acid and a heteropoly acid compound as an additive at least in one of the positive electrode, the negative electrode, the separator, and the electrolyte. | 12-20-2012 |