Patent application number | Description | Published |
20080220574 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed. | 09-11-2008 |
20080237734 | COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FABRICATING THE SAME - A complementary metal-oxide-semiconductor (CMOS) transistor comprising a substrate, a first conductive type MOS transistor, a second conductive type MOS transistor, a buffer layer, a first stress layer and a second stress layer is provided. The substrate has a device isolation structure therein that defines a first active area and a second active area. The first conductive type MOS transistor and the second conductive type MOS transistor are respectively disposed in the first active area and the second active area of the substrate. A first nitride spacer of the first conductive type MOS transistor has a thickness greater than that of a second nitride spacer of the second conductive type MOS transistor. The buffer layer is disposed on the first conductive type MOS transistor. The first stress layer is disposed on the buffer layer. The second stress layer is disposed on the second conductive type MOS transistor. | 10-02-2008 |
20080242031 | METHOD FOR FABRICATING P-CHANNEL FIELD-EFFECT TRANSISTOR (FET) - A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region. | 10-02-2008 |
20090166625 | MOS DEVICE STRUCTURE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device and the structure thereof. The method includes at least the steps of forming a silicon germanium layer by the first selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the second selective epitaxy growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 07-02-2009 |
20090239347 | METHOD OF FORMING MOS DEVICE - The present invention provides a method for forming a metal-oxide-semiconductor (MOS) device. The method includes at least the steps of forming a silicon germanium layer by the selective epitaxy growth process and forming a cap layer on the silicon germanium layer by the selective growth process. Hence, the undesirable effects caused by ion implantation can be mitigated. | 09-24-2009 |
20110097868 | METHOD FOR FABRICATING P-CHANNEL FIELD-EFFECT TRANSISTOR (FET) - A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region. | 04-28-2011 |
20110104864 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a complementary metal oxide semiconductor (CMOS) device is provided. A first conductive type MOS transistor including a source/drain region using a semiconductor compound as major material is formed in a first region of a substrate. A second conductive type MOS transistor is formed in a second region of the substrate. Next, a pre-amorphous implantation (PAI) process is performed to amorphize a gate conductive layer of the second conductive type MOS transistor. Thereafter, a stress-transfer-scheme (STS) is formed on the substrate in the second region to generate a stress in the gate conductive layer. Afterwards, a rapid thermal annealing (RTA) process is performed to activate the dopants in the source/drain region. Then, the STS is removed. | 05-05-2011 |
20110156156 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a substrate, a first stress, and a second stress. The substrate has a first-type MOS transistor, an input/output (I/O) second-type MOS transistor, and a core second-type MOS transistor formed thereon. The first-type and the second-type are opposite conductivity types with respect to each other. The first stress layer is only disposed on the first-type MOS transistor, and the second stress layer is different from the first stress, and is only disposed on the core second-type MOS transistor. The I/O second-type MOS transistor is a type of I/O MOS transistor and without not noly the first stress layer but also the second stress layer disposed thereon, the core second-type MOS transistor is a type of core MOS transistor. | 06-30-2011 |
20110254064 | SEMICONDUCTOR DEVICE WITH CARBON ATOMS IMPLANTED UNDER GATE STRUCTURE - An exemplary semiconductor device includes a substrate, a spacer, a metal silicide layer and carbon atoms. The substrate has a gate structure formed thereon. The spacer is formed on the sidewall of the gate structure. The spacer has a first side adjacent to the gate structure and a second side away from the gate structure. The metal silicide layer is formed on the substrate and adjacent to the second side of the spacer but away from the first side of the spacer. The carbon atoms are formed into the substrate and adjacent to the first side of the spacer but away from the second side of the spacer. | 10-20-2011 |
20120009745 | METHOD FOR FABRICATING FIELD-EFFECT TRANSISTOR - A method for fabricating complimentary metal-oxide-semiconductor field-effect transistor is disclosed. The method includes the steps of: (A) forming a first gate structure and a second gate structure on a substrate; (B) performing a first co-implantation process to define a first type source/drain extension region depth profile in the substrate adjacent to two sides of the first gate structure; (C) forming a first source/drain extension region in the substrate adjacent to the first gate structure; (D) performing a second co-implantation process to define a first pocket region depth profile in the substrate adjacent to two sides of the second gate structure; (E) performing a first pocket implantation process to form a first pocket region adjacent to two sides of the second gate structure. | 01-12-2012 |
20140348416 | STEREO IMAGE RECTIFICATION APPARATUS AND METHOD - A stereo image rectification apparatus includes: an input unit, for receiving a first image from a first camera and a second image from a second camera, wherein the first and the second camera are affine cameras; a feature point determination unit, for determining at least one first feature point on the first image and at least one second feature point on the second image, wherein both the first feature point on the first image and the second feature point on the second image correspond to the same imaginary object; and a warping matrix establishing unit, for establishing a warping matrix for mapping the first image to the second image by: calculating the elements of the warping matrix in regard to the mapping between the x- and y-coordinates of the first feature points and the y-coordinates of the second feature points | 11-27-2014 |
20140348428 | DYNAMIC RANGE-ADJUSTMENT APPARATUSES AND METHODS - A dynamic range-adjustment apparatus is provided. The apparatus includes: an input unit for receiving an original image; an histogram equalization unit, coupled to the input unit, for performing contrast enhancement on the original image to produce a contrast-enhanced image; a factor-determination unit, coupled to the input unit and the histogram equalization unit, for determining a first factor based on the gray level of a pixel of the original image and the tone of the corresponding pixel of the contrast-enhanced image; and an adjustment unit, coupled to the input unit, the histogram equalization unit and the factor-determination unit. | 11-27-2014 |