Patent application number | Description | Published |
20090252931 | REINFORCED ASSEMBLY CARRIER AND METHOD FOR MANUFACTURING THE SAME AS WELL AS METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGES - A reinforced assembly carrier is provided. A supporting frame made of molding compound is formed on the edge area of the upper surface and/or on the edge area of the lower surface of the assembly carrier thereby enhancing the mechanical strength of the assembly carrier. | 10-08-2009 |
20100314744 | SUBSTRATE HAVING SINGLE PATTERNED METAL LAYER EXPOSING PATTERNED DIELECTRIC LAYER, CHIP PACKAGE STRUCTURE INCLUDING THE SUBSTRATE, AND MANUFACTURING METHODS THEREOF - A chip package structure includes a substrate, a die, and a package body. The substrate includes a single patterned, electrically conductive layer, and a patterned dielectric layer adjacent to an upper surface of the electrically conductive layer. A part of a lower surface of the electrically conductive layer forms first contact pads for electrical connection externally. The patterned dielectric layer exposes a part of the upper surface of the electrically conductive layer to form second contact pads. The electrically conductive layer exposes the lower surface of the patterned dielectric layer on a lower periphery of the substrate. The die is electrically connected to the second contact pads, the patterned dielectric layer and the die being positioned on the same side of the electrically conductive layer. The package body is disposed adjacent to the upper surface of the electrically conductive layer and covers the patterned dielectric layer and the die. | 12-16-2010 |
20100320610 | SEMICONDUCTOR PACKAGE WITH SUBSTRATE HAVING SINGLE METAL LAYER AND MANUFACTURING METHODS THEREOF - A semiconductor package includes a substrate, a die, and a package body. The substrate includes: (a) a core including a resin reinforced with fibers; (b) a plurality of openings extending through the core; (c) a dielectric layer; and (d) a single conductive layer disposed between the dielectric layer and the core. Portions of a lower surface of the single conductive layer cover the plurality of openings to form a plurality of first contact pads for electrical connection external to the semiconductor package. Exposed portions of an upper surface of the single conductive layer form a plurality of second contact pads. The die is electrically connected to the plurality of second contact pads, and the package body encapsulates the die. | 12-23-2010 |
20110084370 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts a connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 04-14-2011 |
20110169150 | Semiconductor Package with Single Sided Substrate Design and Manufacturing Methods Thereof - A semiconductor package includes a substrate unit, a die electrically connected to first contact pads, and a package body covering a first patterned conductive layer and the die. The substrate unit includes: (1) the first patterned conductive layer; (2) a first dielectric layer exposing a part of the first patterned conductive layer to form the first contact pads; (3) a second patterned conductive layer; (4) a second dielectric layer defining openings extending from the first patterned conductive layer to the second patterned conductive layer, where the second patterned conductive layer includes second contact pads exposed by the second dielectric layer; and (5) conductive posts extending from the first patterned conductive layer to the second contact pads through the openings, each of the conductive posts filling a corresponding one of the openings. At least one of the conductive posts defines a cavity. | 07-14-2011 |
20120104584 | SEMICONDUCTOR DEVICE PACKAGES WITH PROTECTIVE LAYER AND RELATED METHODS - A Quad Flat No Leads (QFN) package includes a lead frame, a chip, an encapsulant, and a protective layer. The lead frame includes a plurality of leads. Each of the leads has a lower surface that is divided into a contact area and a non-contact area. The chip is configured on and electrically connected to the lead frame. The encapsulant encapsulates the chip and the leads and fills spaces between the leads. The contact areas and the non-contact areas of the leads are exposed by the encapsulant. The protective layer covers the non-contact areas of the leads. | 05-03-2012 |
20120112338 | HEAT DISSIPATING SEMICONDUCTOR DEVICE PACKAGES AND RELATED METHODS - An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices are attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages. | 05-10-2012 |
20120217642 | SEMICONDUCTOR DEVICE PACKAGES HAVING A SIDE-BY-SIDE DEVICE ARRANGEMENT AND STACKING FUNCTIONALITY - A semiconductor device package including a substrate, a first device module, a second device module, and an package body. The first device module and the second device module are disposed side-by-side on a carrier surface of the substrate. The first device module includes first connecting elements provided with a first pitch. The second device module includes second connecting elements provided with a second pitch. The first pitch is different from the second pitch. The package body is disposed on the carrier surface and covers the first chip module and the second chip module. The package body includes first openings exposing the first connecting elements and second openings exposing the second connecting elements. | 08-30-2012 |
20140021636 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 01-23-2014 |
20140084475 | SEMICONDUCTOR PACKAGE SUBSTRATES HAVING PILLARS AND RELATED METHODS - The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern. | 03-27-2014 |
20140151876 | SEMICONDUCTOR PACKAGE AND PROCESS FOR FABRICATING SAME - A package carrier includes: (a) a dielectric layer defining a plurality of openings; (b) patterned electrically conductive layer, embedded in the dielectric layer and disposed adjacent to a first surface of the dielectric layer; (c) a plurality of electrically conductive posts, disposed in respective ones of the openings, wherein the openings extend between a second surface of the dielectric layer to the patterned electrically conductive layer, the electrically conductive posts are connected to the patterned electrically conductive layer, and an end of each of the electrically conductive posts has a curved profile and is faced away from the patterned electrically conductive layer; and (d) a patterned solder resist layer, disposed adjacent to the first surface of the dielectric layer and exposing portions of the patterned electrically conductive layer corresponding to contact pads. A semiconductor package includes the package carrier, a chip, and an encapsulant covering the chip and the package carrier. | 06-05-2014 |
20140308778 | HEAT DISSIPATING SEMICONDUCTOR DEVICE PACKAGES AND RELATED METHODS - An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages. | 10-16-2014 |
20140346670 | SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF - A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer. | 11-27-2014 |