Patent application number | Description | Published |
20100222174 | WOBBLE MECHANISM - A wobble mechanism, in particular for a two-part adjustment fitting of a vehicle seat, is provided with a flat housing with internal toothing and with an oscillating wheel with external toothing, which is arranged within the housing and is eccentrically rotatable around a center axis of the housing. The external toothing of the oscillating wheel engages with the internal toothing of the housing. The housing is divided into at least two housing parts along a dividing plane. | 09-02-2010 |
20100295349 | METHOD FOR AUTOMATICALLY ADJUSTING A HEADREST OF A MOTOR VEHICLE SEAT, AND DEVICE FOR CARRYING OUT SAID METHOD - A method for automatically adjusting a headrest of a motor vehicle seat, which can individually be adjusted to a passenger occupying the motor vehicle seat with a sensor array and an electronically controlled adjusting device such that the headrest is in an adjusted position which is defined as optimal as possible for absorbing acceleration forces acting on the head of the passenger in a case of crash is provided. The adjusting device can be controlled via a control unit which evaluates at least one signal of at least one sensor, in order to control the adjustment of the headrest with the adjusting mean. At least one signal from the at least one sensor serves to detect an occupation of the motor vehicle seat by a passenger. | 11-25-2010 |
20110062737 | MOTOR VEHICLE REAR SEAT - A rear seat for a motor vehicle with a seat part and a backrest which is upright in a seating position and folded down in a loading position, and in the loading position increases the loading space floor with its rear side facing a loading space of the motor vehicle is provided. The seat part is connected with at least one electromotive drive for translatorily adjusting and/or folding down the seat part from the seating position into the loading position and for translatorily returning and/or folding back the seat part from the loading position into the seating position. | 03-17-2011 |
20110278892 | VEHICLE SEAT COMPRISING A PLURALITY OF STRUCTURAL OR RETAINING PARTS AS WELL AS A METHOD FOR PRODUCING STRUCTURAL OR RETAINING PARTS OF SUCH A VEHICLE SEAT - The invention relates to a vehicle seat and to a method for producing said vehicle seat, in particular for motor vehicles, comprising a plurality of structural or retaining parts which are joined together or to a further part in at least one joining region, the join being produced by friction welding in at least one of the joining regions. | 11-17-2011 |
20130180348 | ADJUSTMENT DRIVE FOR AN ADJUSTMENT DEVICE OF A MOTOR VEHICLE SEAT - An adjustment drive for an adjusting device of a motor vehicle seat includes a drive motor | 07-18-2013 |
Patent application number | Description | Published |
20090052431 | METHOD AND DEVICE FOR PACKET BASED CLOCK RECOVERY - A master clock in a first radio network unit, configured for sending data packets at predetermined time intervals, is synchronized with a slave clock in a second radio network unit. To provide a method for packet based clock recovery being able to achieve the desired accuracy within an acceptable time while avoiding a high computational complexity, the following procedure is used. An estimate value is determined for the transmission delay time for each data packet in a predetermined set of data packets. At least one pair of data packets is selected that has a minimum estimate value for the transmission delay time. A difference of the reception times of the selected pair of data packets is determined. Finally, a clock estimate procedure is performed using the difference of the reception times of the selected pair of data packets to determine the quantity representative of the clock frequency difference and/or the clock time offset. | 02-26-2009 |
20120063413 | Communication Resource Allocation Strategy - A scheduling processor allocates a time slot of a communication protocol to a user equipment for data transmission based on received control data of the same or another user equipment in a current time slot and received user data of the same or another user equipment in a preceding time slot, while ignoring user data of the same or any other user equipment received in the current time slot. The scheduling processor also allocates a frequency resource to the user equipment. A control channel managing processor allocates signaling resources on a control channel for the submission of control information to the user equipment, which informs of the time slot allocated by the time domain scheduling processor as well as of the frequency resource allocated by the frequency domain scheduling processor. | 03-15-2012 |
20130107782 | Scheduling of User Terminals in Communication Network | 05-02-2013 |
20140293952 | Scheduling a Transmission of Data - Transmission of data is scheduled via a first communication channel within a first cell of a cellular network. A first base station is assigned to the first cell. A user equipment is served by the first base station, and the first communication channel is divided into subframes. The cellular network includes a second base station assigned to a second cell, wherein the second base station uses a second communication channel divided into subframes, and a part of the subframes is unscheduled by the second base station due to a predefined muting pattern. The first base station determines a first subframes of the first communication channel related in time with the unscheduled subframes of the second communication channel, and schedules transmission of data between the first base station and the user equipment via the first communication channel so that the data is transmitted in the determined first subframes. | 10-02-2014 |
20140328316 | Rate Capping with Multiple Carrier Aggregation Schedulers - Requests for carrier aggregation scheduling for a user equipment are received from a first cell used for carrier aggregation and n second cells. The requests include a first scheduling decision of the first cell and n second scheduling decisions of the n second cells. It is checked whether or not the requests exceed limits of the user equipment, and the n second scheduling decisions are modified according to predefined rules such that the requests do not exceed the limits. Limits of the user equipment are increased by a margin, the increased limits are split onto active cells of the first and n second cells according to a predefined rule, and the margin is controlled dependent on whether the increased and split limits are exceeded or not by the requests. If they are exceeded, the n second scheduling decisions may be modified. | 11-06-2014 |
20150050935 | Controlling a Radio Resource Control Connection Between a Base Station and a User Equipment - It is described a method for controlling a radio resource control connection between a base station and a user equipment, wherein a radio resource control connection between the base station and the user equipment is established for exchanging control messages between the base station and the user equipment the control messages being required for an application running on the user equipment. The method includes determining a first value being indicative for a mobility characteristic of the user equipment and a second value being indicative for a data traffic characteristic of the user equipment, comparing the first value and the second value, setting a release timer based on the comparison, and controlling the radio resource control connection based on the release timer, wherein the radio resource control connection will end upon expiry of the release timer. | 02-19-2015 |
20150063222 | COORDINATED SCHEDULING WITH ADAPTIVE MUTING - Systems, methods, apparatuses, and computer program products relating to coordinated scheduling with adaptive muting are provided. One method comprises transmitting, by a network element, calculated impact information for a cell of the network element when taking an action related to a cell of the network element and/or taking an action related to a cell of a second network element. The method may also comprise transmitting a request for taking the action related to the cell of the second network element under certain circumstances | 03-05-2015 |
20150065108 | COORDINATED SCHEDULING WITH ADAPTIVE MUTING - Systems, methods, apparatuses, and computer program products relating to coordinated scheduling with adaptive muting are provided. One method comprises transmitting, by a network element, calculated impact information for a cell of the network element when taking an action related to a cell of the network element and/or taking an action related to a cell of a second network element. The method may also comprise transmitting a request for taking the action related to the cell of the second network element under certain circumstances | 03-05-2015 |
Patent application number | Description | Published |
20110320514 | DECIMAL ADDER WITH END AROUND CARRY - Binary code decimal (BCD) arithmetic add/subtract operations on two BCD numbers independent of which BCD number is of a greater magnitude include, responsive to the BCD arithmetic add/subtract operation being a subtract operation, performing a BCD arithmetic subtraction operation on a first BCD number and a second BCD number, the first BCD number having a first magnitude and the second BCD number having a second magnitude. The first magnitude is greater than, equal to, or less than the second magnitude. The performing includes: in parallel to a carry generation, partial sums or partial differences of the first and second BCD numbers are computer such that a final result in signed magnitude form is selectable from the partial sums or differences based on carry information without any post processing steps. | 12-29-2011 |
20130173681 | Range Check Based Lookup Tables - Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values. | 07-04-2013 |
20130173683 | Range Check Based Lookup Tables - Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values. | 07-04-2013 |
20140095568 | Fused Multiply-Adder with Booth-Encoding - A fused multiply-adder is disclosed. The fused multiply-adder includes a Booth encoder, a fraction multiplier, a carry corrector, and an adder. The Booth encoder initially encodes a first operand. The fraction multiplier multiplies the Booth-encoded first operand by a second operand to produce partial products, and then reduces the partial products into a set of redundant sum and carry vectors. The carry corrector then generates a carry correction factor for correcting the carry vectors. The adder adds the redundant sum and carry vectors and the carry correction factor to a third operand to yield a final result. | 04-03-2014 |
Patent application number | Description | Published |
20100058266 | 3-Stack Floorplan for Floating Point Unit - A 3-stack floorplan for a floating point unit includes: an aligner located in the center of the floating point unit; a frontend located directly above the aligner; a multiplier located directly below the frontend and next to the aligner; an adder located directly next to the multiplier and directly below the aligner; a normalizer located directly above the adder; and a rounder located directly above the normalizer. | 03-04-2010 |
20100095099 | SYSTEM AND METHOD FOR STORING NUMBERS IN FIRST AND SECOND FORMATS IN A REGISTER FILE - A system and a method for storing numbers in a register file are provided. The system and the method store single precision numbers in double precision format in a register file that is shared between floating point computational units and computational units not supporting floating point numbers. | 04-15-2010 |
20100100713 | FAST FLOATING POINT COMPARE WITH SLOWER BACKUP FOR CORNER CASES - A floating point processor unit executes a floating point compare instruction with two operands of the same or different precision by comparing the two operands in integer format, which speeds up the execution of the floating point compare instruction significantly. The floating point processor now executes the floating point compare instruction at least twice as fast or faster (e.g., two clock cycles instead of five clock cycles in the prior art) for nearly most operand cases (e.g., 99% of all cases). Only the rare corner cases require additional operations on one of the operands and thus require additional cycles of execution time because the integer compare operation will not work for these corner cases. This is due to the fact that one operand is a single precision subnormal number in an unnormalized representation (i.e., has two representations) and the other operand is in the SP subnormal range such that the integer compare operation will fail. | 04-22-2010 |
20110320512 | Decimal Floating Point Mechanism and Process of Multiplication without Resultant Leading Zero Detection - A decimal multiplication mechanism for fixed and floating point computation in a computer having a coefficient mechanism without resulting leading zero detection (LZD) and process which assumes that the final product will be M+N digits in length and performs all calculations based on this assumption. Least significant digits that would be truncated are no longer stored, but retained as sticky information which is used to finalize the result product. Once the computation of the product is complete, a final check based on the examination of key bits observed during partial product accumulation is used to determine if the final product is truly M+N digits in length, or M+N−1 digits. If the latter is true, then corrective final product shifting is employed to obtain the proper result. This eliminates the need for dedicated leading zero detection hardware used to determine the number of significant digits in the final product. The corrective final product shifting also incorporates adjustments to the coefficient of the product when the product's exponent is at its extremes and the final product must be brought to be within the precision and range of a given format. | 12-29-2011 |
Patent application number | Description | Published |
20100146027 | RESIDUE CALCULATION WITH BUILT-IN CORRECTION IN A FLOATING POINT UNIT - A residue generator for calculation and correction of a residue value. The residue generator includes a residue-generation tree connected with an operand register at an input of the residue generator including a plurality of register-bits receiving and carrying bits of numerical data. The residue-generation tree includes a multiplexer connected with respective register-bits which carry unused bits, and selectively providing logical zeros or a correction value when provided, at the respective register-bits carrying the unused bits, a plurality of decoders, each decoder receiving the bits of numerical data from the respective registers-bits including the logical zeros or the correction value when provided and decoding the numerical data, and a plurality of residue condensers, receiving the decoded numerical data from the decoders including the logical zeros or the correction value when provided, and calculating the residue value and correcting while calculating the residue value using the correction value when provided by the multiplexer. | 06-10-2010 |
20130124588 | ENCODING DENSELY PACKED DECIMALS - According to one aspect of the present disclosure, a method and technique for encoding densely packed decimals is disclosed. The method includes: executing a floating point instruction configured to perform a floating point operation on decimal data in a binary coded decimal (BCD) format; determining whether a result of the operation includes a rounded mantissa overflow; and responsive to determining that the result of the operation includes a rounded mantissa overflow, compressing a result of the operation from the BCD-formatted decimal data to decimal data in a densely packed decimal (DPD) format by shifting select bit values of the BCD formatted decimal data by one digit to select bit positions in the DPD format. | 05-16-2013 |
20130339417 | RESIDUE-BASED EXPONENT FLOW CHECKING - A technique for checking an exponent calculation for an execution unit that supports floating point operations includes generating, using a residue prediction circuit, a predicted exponent residue for a result exponent of a floating point operation. The technique also includes generating, using an exponent calculation circuit, the result exponent for the floating point operation and generating, using the residue prediction circuit, a result exponent residue for the result exponent. Finally, the technique includes comparing the predicted exponent residue to the result exponent residue to determine whether the result exponent generated by the exponent calculation circuit is correct and, if not, signaling an error. | 12-19-2013 |
20130339802 | DYNAMIC HARDWARE TRACE SUPPORTING MULTIPHASE OPERATIONS - A method and system for tracing in a data processing system. The method includes receiving a plurality of signals associated with an operation during execution of the operation. The method also includes, in response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selecting and outputting as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selecting and outputting as the trace signal a second signal of the plurality of signals. | 12-19-2013 |
20140095941 | DYNAMIC HARDWARE TRACE SUPPORTING MULTIPHASE OPERATIONS - A method and system for tracing in a data processing system. The method includes receiving a plurality of signals associated with an operation during execution of the operation. The method also includes, in response to an indication that the operation is a multiphase operation, during execution of the operation, selection logic, during a first phase of the multiphase operation, selecting and outputting as a trace signal a first signal of the plurality of signals, and during a second phase of the multiphase operation, selecting and outputting as the trace signal a second signal of the plurality of signals. | 04-03-2014 |
20140149481 | Decimal Multi-Precision Overflow and Tininess Detection - An approach is provided in which a processor includes an adder that concurrently generates one or more intermediate results and a boundary indicator based upon instructions retrieved from a memory area. The boundary indicator indicates whether a collective result generated from the intermediate results is within a boundary precision value. | 05-29-2014 |
20140164463 | EXPONENT FLOW CHECKING - A technique for checking an exponent calculation for an execution unit that supports floating point operations includes generating, using a residue prediction circuit, a predicted exponent residue for a result exponent of a floating point operation. The technique also includes generating, using an exponent calculation circuit, the result exponent for the floating point operation and generating, using the residue prediction circuit, a result exponent residue for the result exponent. Finally, the technique includes comparing the predicted exponent residue to the result exponent residue to determine whether the result exponent generated by the exponent calculation circuit is correct and, if not, signaling an error. | 06-12-2014 |