Kranich
Axel Kranich, Hamburg DE
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20140345131 | ELECTRICALLY CONDUCTIVE PIN CONNECTION - The present disclosure relates to an electrically conductive pin connection, including a first electrically conductive contact component which has a first hole, a second electrically conductive contact component which is in contact with the first electrically conductive contact component and which has a second hole, a connecting pin which has a pin head and which is guided through the first and second holes for connecting the first electrically conductive contact component and the second electrically conductive contact component, and a plurality of electrically conductive wires which are arranged in the holes between the edges of the holes and the connecting pin, wherein the electrically conductive wires are bent in such a way that they are clamped between the pin head of the connecting pin and the first electrically conductive contact component. | 11-27-2014 |
Klaus Kranich, Freiberg DE
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20130298709 | DUAL COUPLING GEAR MECHANISM - Dual coupling gear mechanism for a motor vehicle, having a first input shaft and a second input shaft and having a first and a second countershaft, the input shafts and the counter-shafts being connected to each other by means of a plurality of shiftable wheel sets in order to establish at least seven forward gear stages and at least one reverse gear stage. At least one wheel set has a fixed wheel which is connected to one of the input shafts and two loose wheels which are rotatably supported on the first and on the second counter-shaft, respectively, and which are in engagement with the fixed wheel. An electric engine is connected to a loose wheel of one of the wheel sets or can be connected thereto by means of a shift clutch. | 11-14-2013 |
Mathias Kranich, Albbruck DE
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20140177477 | UTILITY COMMUNICATION METHOD AND SYSTEM - An exemplary method and system of the present disclosure use the Parallel Redundancy Protocol PRP (IEC 62439-3) for traffic duplication and redundant transport of the duplicated traffic in a single packet-switched wide-area communication network including a plurality of nodes interconnected via inter-node links in a meshed topology. The method involves identifying, between a send and receive node, two distinct communication paths with no link or node in common except for the send and receive node, and configuring the send and receive nodes to operate according to the Parallel Redundancy Protocol PRP. At any time during regular operation, and for any critical message to be transmitted from the send to the receive node, two redundant packets can be generated, and each of the redundant packets is sent via one of the two communication paths, resulting in an increased availability of the communication network without incurring the cost of full network duplication. | 06-26-2014 |
Michael Kranich, Besigheim DE
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20090050304 | Heat exchanger for motor vehicles - Disclosed is a heat exchanger for motor vehicles, comprising two spaced-apart manifold devices ( | 02-26-2009 |
20090126920 | Heat exchanger for a motor vehicle - Disclosed herein is a heat exchanger with tubes ( | 05-21-2009 |
20100116474 | HEAT EXCHANGER - A heat exchanger is provided, particularly for a heating or air conditioning system for motor vehicles, comprising at least one inlet channel and at least one outlet channel and at least one collector, which has at least two metal sheets or plates abutting each other, and a flow device, through which a first medium can flow, while a second medium can flow around said flow device. The first medium is distributed by an inlet channel to the collector and to the flow device and can be conducted to an outlet channel, whereby at least one further channel for distributing the coolant is provided, which is connected in a communicating manner via at least one opening to the inlet channel. | 05-13-2010 |
Tim Kranich, Braunschweig DE
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20140089642 | METHODS AND SYSTEMS FOR PERFORMING A REPLAY EXECUTION - One or more embodiments may provide a method for performing a replay. The method includes initiating execution of a program, the program having a plurality of sets of instructions, and each set of instructions has a number of chunks of instructions. The method also includes intercepting, by a virtual machine unit executing on a processor, an instruction of a chunk of the number of chunks before execution. The method further includes determining, by a replay module executing on the processor, whether the chunk is an active chunk, and responsive to the chunk being the active chunk, executing the instruction. | 03-27-2014 |
20140189256 | PROCESSOR WITH MEMORY RACE RECORDER TO RECORD THREAD INTERLEAVINGS IN MULTI-THREADED SOFTWARE - A processor includes a first core to execute a first software thread, a second core to execute a second software thread, and shared memory access monitoring and recording logic. The logic includes memory access monitor logic to monitor accesses to memory by the first thread, record memory addresses of the monitored accesses, and detect data races involving the recorded memory addresses with other threads. The logic includes chunk generation logic is to generate chunks to represent committed execution of the first thread. Each of the chunks is to include a number of instructions of the first thread executed and committed and a time stamp. The chunk generation logic is to stop generation of a current chunk in response to detection of a data race by the memory access monitor logic. A chunk buffer is to temporarily store chunks until the chunks are transferred out of the processor. | 07-03-2014 |
20140281274 | SHARED MEMORY INTERLEAVINGS FOR INSTRUCTION ATOMICITY VIOLATIONS - A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary. | 09-18-2014 |
Uwe Kranich, Kirchheim DE
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20080244137 | PROCESSOR COMPRISING A FIRST AND A SECOND MODE OF OPERATION AND METHOD OF OPERATING THE SAME - A processor comprises a first mode of operation and a second mode of operation. A state of the processor in the first mode of operation comprises a first plurality of variables. The first plurality of variables comprises a return address. A state of the processor in the second mode of operation comprises a second plurality of variables in addition to the first plurality of variables. The processor is configured to perform, in case of an interrupt or exception occurring during the second mode of operation, the steps of saving the second plurality of variables and the return address to a buffer memory, replacing the return address with an address of a trampoline instruction, and switching into the first mode of operation. These steps are performed independently of an operating system. The trampoline instruction is adapted to switch the processor from the first mode of operation to the second mode of operation, to read the second plurality of variables and the return address from the buffer memory and to jump to the return address. | 10-02-2008 |
20080301408 | SYSTEM COMPRISING A PLURALITY OF PROCESSORS AND METHOD OF OPERATING THE SAME - A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables. | 12-04-2008 |