Patent application number | Description | Published |
20080299681 | MULTI-STEP DEPOSITION CONTROL - For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process parameters comprises at least one process parameter. The method comprises controllably generating an actual value for at least one first process parameter by taking into account at least one previous value of the respective first process parameter, wherein each first process parameter is a process parameter of said at least two sets of process parameters. | 12-04-2008 |
20090325378 | REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PERFORMING A DEPOSITION/ETCH CYCLE DURING BARRIER DEPOSITION - A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region. | 12-31-2009 |
20100109131 | REDUCED WAFER WARPAGE IN SEMICONDUCTORS BY STRESS ENGINEERING IN THE METALLIZATION SYSTEM - In complex metallization systems of sophisticated semiconductor devices, appropriate stress compensation mechanisms may be implemented in order to reduce undue substrate deformation during the overall manufacturing process. For example, additional dielectric material and/or functional layers of one or more metallization layers may be provided with appropriate internal stress levels so as to maintain substrate warpage at a non-critical level, thereby substantially reducing yield losses in the manufacturing process caused by non-reliable attachment of substrates to substrate holders in process and transport tools. | 05-06-2010 |
20100244028 | TEST SYSTEM AND METHOD OF REDUCING DAMAGE IN SEED LAYERS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - During the formation of a complex metallization system, the influence of a manufacturing environment on sensitive barrier/seed material systems may be monitored or controlled by using an appropriate test pattern and applying an appropriate test strategy. For example, actual probe and reference substrates may be prepared and may be processed with and without exposure to the manufacturing environment of interest, thereby enabling an efficient evaluation of one or more parameters of the environment. Furthermore, an “optimized” manufacturing environment may be obtained on the basis of the test strategy disclosed herein. | 09-30-2010 |
20120160415 | MULTI-STEP DEPOSITION CONTROL - For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each set of process parameters comprises at least one process parameter. The method comprises controllably generating an actual value for at least one first process parameter by taking into account at least one previous value of the respective first process parameter, wherein each first process parameter is a process parameter of said at least two sets of process parameters. | 06-28-2012 |
20130203266 | Methods of Forming Metal Nitride Materials - Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer. | 08-08-2013 |
20140024213 | PROCESSES FOR FORMING INTEGRATED CIRCUITS WITH POST-PATTERNING TREAMENT - Processes for forming an integrated circuit are provided. In an embodiment, a process for forming an integrated circuit includes forming a low-k dielectric layer overlying a base substrate. An etch mask is patterned over the low-k dielectric layer. A recess is etched into the low-k dielectric layer through the etch mask to expose a recess surface within the recess. The low-k dielectric layer and the base substrate are annealed after etching. Annealing is conducted in an annealing environment, such as in an annealing furnace that provides the annealing environment. The recess surface is exposed to the annealing environment. An electrically-conductive material is deposited in the recess after annealing to form an embedded electrical interconnect. | 01-23-2014 |
20140273436 | METHODS OF FORMING BARRIER LAYERS FOR CONDUCTIVE COPPER STRUCTURES - One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in at least the trench/via, after forming said barrier layer, performing at least one process operation to introduce manganese into the barrier layer and thereby define a manganese-containing barrier layer, forming a substantially pure copper-based seed layer above the manganese-containing barrier layer, depositing a bulk copper-based material above the copper-based seed layer so as to overfill the trench/via, and removing excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. | 09-18-2014 |
20140349478 | METHOD INCLUDING AN ETCHING OF A PORTION OF AN INTERLAYER DIELECTRIC IN A SEMICONDUCTOR STRUCTURE, A DEGAS PROCESS AND A PRECLEAN PROCESS - A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas. | 11-27-2014 |
Patent application number | Description | Published |
20080242963 | SYSTEM, TOOLS, DEVICES AND A PROGRAM FOR DIABETES CARE - A method for diabetes care, the method (which also may be referred to as, involve or incorporate at least one of a tool, device or program) allowing for the characterization of the relevance of errors of parameters affecting glucose concentration on a postprandial glucose concentration outcome for a person with diabetes mellitusm, wherein the method involves at least one of sensing, determining, calculating, predicting, describing and communicating the effects of potential errors of parameters affecting glucose concentration on postprandial glucose concentration values within a clinically relevant glucose range. | 10-02-2008 |
20100235316 | SYSTEM, TOOLS, DEVICES AND A PROGRAM FOR DIABETES CARE - A method for diabetes care, the method (which also may be referred to as, involve or incorporate at least one of a tool, device or program) allowing for the characterization of the relevance of errors of parameters affecting glucose concentration on a postprandial glucose concentration outcome for a person with diabetes mellitusm, wherein the method involves at least one of sensing, determining, calculating, predicting, describing and communicating the effects of potential errors of parameters affecting glucose concentration on postprandial glucose concentration values within a clinically relevant glucose range. | 09-16-2010 |