Kornegay, US
Adam T. Kornegay, Irvine, CA US
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20100169209 | SYSTEM AND METHOD FOR INTERACTIVELY SIMULATING A CREDIT-WORTHINESS SCORE - A system and method is provided to allow a consumer to interactively explore his credit score by submitting hypothetical values based on his actual credit data. The system uses the consumer's real credit data and the submitted hypothetical values to calculate a simulated credit score based on a simulator scorecard. The consumer may then observe the changes in the resultant scores. The system and the scorecard may utilize fewer data elements than a complete credit-worthiness scorecard and may instead focus on the key elements affecting a consumer's credit score. The system may be implemented in part on a web server or as a stand-alone application. The system may also update the score dynamically as the consumer adjusts the hypothetical values or may require the consumer to affirmatively submit the new hypothetical data. | 07-01-2010 |
20120066116 | SYSTEM AND METHOD FOR INTERACTIVELY SIMULATING A CREDIT-WORTHINESS SCORE - A system and method is provided to allow a consumer to interactively explore his credit score by submitting hypothetical values based on his actual credit data. The system uses the consumer's real credit data and the submitted hypothetical values to calculate a simulated credit score based on a simulator scorecard. The consumer may then observe the changes in the resultant scores. The system and the scorecard may utilize fewer data elements than a complete credit-worthiness scorecard and may instead focus on the key elements affecting a consumer's credit score. The system may be implemented in part on a web server or as a stand-alone application. The system may also update the score dynamically as the consumer adjusts the hypothetical values or may require the consumer to affirmatively submit the new hypothetical data. | 03-15-2012 |
20130173451 | SYSTEM AND METHOD FOR INTERACTIVELY SIMULATING A CREDIT-WORTHINESS SCORE - A system and method is provided to allow a consumer to interactively explore his credit score by submitting hypothetical values based on his actual credit data. The system uses the consumer's real credit data and the submitted hypothetical values to calculate a simulated credit score based on a simulator scorecard. The consumer may then observe the changes in the resultant scores. The system and the scorecard may utilize fewer data elements than a complete credit-worthiness scorecard and may instead focus on the key elements affecting a consumer's credit score. The system may be implemented in part on a web server or as a stand-alone application. The system may also update the score dynamically as the consumer adjusts the hypothetical values or may require the consumer to affirmatively submit the new hypothetical data. | 07-04-2013 |
Adam T. Kornegay, Costa Mesa, CA US
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20130268324 | USING COMMERCIAL SHARE OF WALLET TO RATE INVESTMENTS - Commercial size of spending wallet (“CSoSW”) is the total business spend of a business including cash but excluding bartered items. Commercial share of wallet (“CSoW”) is the portion of the spending wallet that is captured by a particular financial company. A modeling approach utilizes various data sources to provide outputs that describe a company's spend capacity. A mutual fund rating company can use this CSoW/CSoSW modeling approach to predict the performance of funds that invest in a particular industry or sector. In addition, since mutual funds often provide guidelines for selecting stocks, rating companies can use this modeling approach to predict the performance of companies in a fund's portfolio. | 10-10-2013 |
Adam T. Kornegay, Mckinney, TX US
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20100250434 | Computer-Based Modeling of Spending Behaviors of Entities - Time series consumer spending data, point-in-time balance information and consumer panel information provide input to a model for consumer spend behavior on plastic instruments or other financial accounts, from which approximations of spending ability and share of wallet may be reliably identified and utilized to promote additional consumer spending. | 09-30-2010 |
20100250469 | Computer-Based Modeling of Spending Behaviors of Entities - Time series consumer spending data, point-in-time balance information and consumer panel information provide input to a model for consumer spend behavior on plastic instruments or other financial accounts, from which approximations of spending ability and share of wallet may be reliably identified and utilized to promote additional consumer spending. | 09-30-2010 |
20130173359 | METHOD AND APPARATUS FOR ESTIMATING THE SPEND CAPACITY OF CONSUMERS - Time series consumer spending data, point-in-time balance information, internal customer financial data and consumer panel information provides input to a model for consumer spend behavior on plastic instruments or other financial accounts, from which approximations of spending ability may be reliably identified and utilized to promote additional consumer spending. | 07-04-2013 |
Adam Thomas Kornegay, Knoxville, TN US
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20120116950 | SYSTEM AND METHOD FOR GENERATING A FINANCE ATTRIBUTE FROM TRADELINE DATA - Embodiments of a system and method are described for generating a finance attribute. In one embodiment, the systems and methods retrieve raw tradeline data from a plurality of credit bureaus, retrieve industry code data related to each of the plurality of credit bureaus, determine one or more tradeline leveling characteristics that meet at least one pre-determined threshold, and generate a finance attribute using the selected leveling characteristics. | 05-10-2012 |
20130080315 | SYSTEM AND METHOD FOR GENERATING A FINANCE ATTRIBUTE FROM TRADELINE DATA - Embodiments of a system and method are described for generating a finance attribute. In one embodiment, the systems and methods retrieve raw tradeline data from a plurality of credit bureaus, retrieve industry code data related to each of the plurality of credit bureaus, determine one or more tradeline leveling characteristics that meet at least one pre-determined threshold, and generate a finance attribute using the selected leveling characteristics. | 03-28-2013 |
Brandon Kornegay, New Bern, NC US
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20110317738 | TEMPERATURE CABINET SUPPORT STRUCTURE - A framework is provided for positioning a testing cabinet for testing an appliance. The framework includes a base for supporting the appliance; a first side frame attached to the base; a rear frame attached to the base; a second side frame attached to the base and located opposite to the first side frame; and a top frame attached to the first side frame. The first side frame, the rear frame, the second side frame, and the top frame are adapted to hold panels of the testing cabinet in a predetermined position relative to the appliance, and the framework is adapted to hold a side panel of the panels of the testing cabinet in a plurality of different positions. | 12-29-2011 |
20110320041 | OVEN TESTING FIXTURE AND METHOD - A testing apparatus is provided for opening and closing a door of an appliance being tested. The apparatus includes a framework; a first actuator attached to the framework, the first actuator having a retracted position and an extended position; a first attaching bar attached to the first actuator and to the door; and a controller for controlling the first actuator such that the first actuator causes the door to move to an open position when the actuator moves from a first one of the extended position and the retracted position to the other of the extended position and the retracted position, and the first actuator causes the door to move to a closed position when the actuator moves from the other of the extended position and the retracted position to the first one of the extended position and the retracted position. | 12-29-2011 |
Janet Kornegay, Alameda, CA US
Patent application number | Description | Published |
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20090155773 | High-Risk Human Papillomavirus Detection - This invention provides compositions and methods for detecting HPV in a sample. This invention also provides related kits, systems, and computers. | 06-18-2009 |
20120009562 | High-Risk Human Papillomavirus Detection - This invention provides compositions and methods for detecting HPV in a sample. This invention also provides related kits, systems, and computers. | 01-12-2012 |
20120009563 | High-Risk Human Papillomavirus Detection - This invention provides compositions and methods for detecting HPV in a sample. This invention also provides related kits, systems, and computers. | 01-12-2012 |
20120009564 | High-Risk Human Papillomavirus Detection - This invention provides compositions and methods for detecting HPV in a sample. This invention also provides related kits, systems, and computers. | 01-12-2012 |
Kyle Kornegay, Las Vegas, NV US
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20150209654 | RECONFIGURABLE PLAYING CARDS AND GAME DISPLAY DEVICES - The invention is directed to a reconfigurable gaming tables and playing cards, such as card devices including thin, planar display devices in communication with a processing device for randomly selecting card images stored in a data storage device for display on the display devices. | 07-30-2015 |
Marcus L. Kornegay, Morrisville, NC US
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20080215818 | STRUCTURE FOR SILENT INVALID STATE TRANSITION HANDLING IN AN SMP ENVIRONMENT - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design can be provided. The design structure includes a symmetric multiprocessing (SMP) system. The system includes a plurality of nodes. Each of the nodes includes a node controller and a plurality of processors cross-coupled to one another. The system also includes at least one cache directory coupled to each node controller, and, invalid state transition logic coupled to each node controller. The invalid state transition logic includes program code enabled to identify an invalid state transition for a cache line in a local node, to evict a corresponding cache directory entry for the cache line, and to forward an invalid state transition notification to a node controller for a home node for the cache line in order for the home node to evict a corresponding cache directory entry for the cache line. | 09-04-2008 |
20080313427 | DIRECTORY-BASED DATA TRANSFER PROTOCOL FOR MULTIPROCESSOR SYSTEM - A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state. | 12-18-2008 |
Marcus L. Kornegay, Charlotte, NC US
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20100325367 | Write-Back Coherency Data Cache for Resolving Read/Write Conflicts - A write-back coherency data cache for temporarily holding cache lines. Upon receiving a processor request for data, a determination is made from a coherency directory whether a copy of the data is cached in a write-back cache located in a memory controller hardware. The write-back cache holds data being written back to main memory for a period of time prior to writing the data to main memory. If the data is cached in the write-back cache, the data is removed from the write-back cache and forwarded to the requesting processor. The cache coherency state in the coherency directory entry for the data is updated to reflect the current cache coherency state of the data based on the requesting processor's intended use of the data. | 12-23-2010 |
Marcus L. Kornegay, Research Triangle Park, NC US
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20100332763 | APPARATUS, SYSTEM, AND METHOD FOR CACHE COHERENCY ELIMINATION - An apparatus, system, and method are disclosed for improving cache coherency processing. The method includes determining that a first processor in a multiprocessor system receives a cache miss. The method also includes determining whether an application associated with the cache miss is running on a single processor core and/or whether the application is running on two or more processor cores that share a cache. A cache coherency algorithm is executed in response to determining that the application associated with the cache miss is running on two or more processor cores that do not share a cache, and is skipped in response to determining that the application associated with the cache miss is running on one of a single processor core and two or more processor cores that share a cache. | 12-30-2010 |
Marcus Lathan Kornegay, Morrisville, NC US
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20080215815 | SYSTEM AND METHOD OF IMPROVING TASK SWITCHING AND PAGE TRANSLATION PERFORMANCE UTILIZING A MULTILEVEL TRANSLATION LOOKASIDE BUFFER - A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries. | 09-04-2008 |
Marcus Lathan Kornegay, Durham, NC US
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20090193196 | METHOD AND SYSTEM FOR CACHE EVICTION - The proposed system and associated algorithm when implemented improves the processor cache miss rates and overall cache efficiency in multi-core environments in which multiple CPU's share a single cache structure (as an example). The cache efficiency will be improved by tracking CPU core loading patterns such as miss rate and minimum cache line load threshold levels. Using this information along with existing cache eviction method such as LRU, results in determining which cache line from which CPU is evicted from the shared cache when a capacity conflict arises. This methodology allows one to dynamically allocate shared cache entries to each core within the socket based on the particular core's frequency of shared cache usage. | 07-30-2009 |