Patent application number | Description | Published |
20130159638 | INFORMATION PROCESSING APPARATUS AND MEMORY ACCESS METHOD - A node includes a first converting unit that performs conversion between a logical address and a physical address. The node includes a second converting unit that performs conversion between the physical address and processor identification information for identifying a processor included in a each of a plurality of nodes. The node includes a transmitting unit that transmits transmission data including the physical address and the processor identification information for accessing a storing area indicated by the physical address. The node includes a local determining unit that determines whether an access, indicated by the transmission data received from another nodes, is an access to a local area or an access to a shared area based on the physical address included in the transmission data received by the receiving unit. | 06-20-2013 |
20130170334 | INFORMATION PROCESSING APPARATUS, COMPUTER-READABLE RECORDING MEDIUM, AND CONTROL METHOD - An abnormality detection unit provided in at least one node among a plurality of nodes included in an information processing apparatus detects abnormality in a data transmission path of data transmission using a shared memory area sharable in a single node and other node, which is included in the storage unit provided in the single node or other nodes. An error information generation unit provided in the single node generates error information, based on the abnormality detected by the abnormality detection unit, and generates an interrupt with respect to a processor within a self node. The processor provided in the single node performs recovery processing, based on the error information according to the interrupt. | 07-04-2013 |
20130173867 | INFORMATION PROCESSING APPARATUS AND UNAUTHORIZED ACCESS PREVENTION METHOD - An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node. | 07-04-2013 |
20130174161 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING INFORMATION PROCESSING APPARATUS - A hardware thread causes a SleepID register of a WAKEUP signal generation unit to store a SleepID that identifies the hardware thread when suspending a process due to waiting for a process by another CPU. The WAKEUP signal generation unit causes the WAKEUP data register of the WAKEUP signal generation unit to store a SleepID notified by a node when a process that the hardware thread waits ends. The WAKEUP signal generation unit outputs a WAKEUP signal that cancels the stop of the hardware thread to the hardware thread when the SleepIDs of the SleepID register and the WAKEUP data register agree with each other. | 07-04-2013 |
20130174224 | INFORMATION PROCESSING APPARATUS AND UNAUTHORIZED ACCESS PREVENTION METHOD - An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node. | 07-04-2013 |
20130227219 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND ARITHMETIC METHOD - An processor includes a cache memory that temporarily retains data stored in a main storage. The processor includes a processing unit that executes an application by using the data retained in the cache memory. The processor includes a storing unit that stores therein update information indicating data that has been updated by the processing unit within the time period specified by the application executed by the processing unit. The processor includes a write back unit that, when the time period specified by the application ends, writes back, to the main storage from the cache memory, data that is from among the data retained in the cache memory and that is indicated by the update information stored in the storing unit. | 08-29-2013 |
20130227224 | INFORMATION PROCESSING APPARATUS, CONTROL METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - At least one node of a plurality of nodes in an information processing apparatus executes the following processing for data included in a memory of one node or other nodes and stored in a shared memory area which the node and the other nodes access. That is, the node detects an ICE which occurs over a predetermined number of times within a predetermined time or a PCE which occurs at a single location in the shared memory area. When the error is detected, the node performs control to prevent the node and the other nodes from accessing the shared memory. The node recovers the data in a memory area different from the shared memory area. The node notifies information about the different memory area to the other nodes. The node performs control to resume the access to the data from the node and the other nodes. | 08-29-2013 |
20130262783 | INFORMATION PROCESSING APPARATUS, ARITHMETIC DEVICE, AND INFORMATION TRANSFERRING METHOD - An information processing apparatus including a plurarity of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier. | 10-03-2013 |
20140068299 | PROCESSOR, INFORMATION PROCESSING APPARATUS, AND POWER CONSUMPTION MANAGEMENT METHOD - When a result of detection by a current sensor | 03-06-2014 |
Patent application number | Description | Published |
20090095085 | Defect Detection Method of Turbine Generator End Ring - A defect detection method of a turbine generator end ring includes a first ultrasonic testing step of conducting ultrasonic testing by an angle beam technique to the turbine generator end ring, a second ultrasonic testing step of conducting, when an indication echo is detected by the first ultrasonic testing step, ultrasonic testing by a focusing straight beam technique to a portion of the turbine generator end ring from which an indication echo is detected and an interpretation step of interpreting whether the indication echo is a defect echo or a false echo based on a testing result by the second ultrasonic testing step. | 04-16-2009 |
20090320600 | FLAW DETECTION TESTING METHOD - There is provided a flaw detection testing method applied to a slot dovetail portion of a turbine generator rotor shaft. The flaw detection testing method includes an angle determining step of determining a slot angle of the slot dovetail portion using a variable-angle ultrasonic probe, a flaw detection performing step of, on the basis of a determination result in the angle determining step, using an angle ultrasonic probe or a phased array probe to perform flaw detection to detect a flaw in the slot dovetail portion, and a flaw depth measuring step of, when the flaw is detected in the flaw detection performing step, using an angle ultrasonic probe to measure a depth of the flaw from a surface of the slot dovetail portion. | 12-31-2009 |
20100139107 | METHOD AND JIG FOR DEVICE FOR MEASURING THREE-DIMENSIONAL SHAPE OF CONNECTION ASSEMBLY OF STATOR COIL IN TURBINE GENERATOR - A method of measuring a three-dimensional shape of a connection assembly of a stator coil in a turbine generator, includes first measuring a three-dimensional shape of a measurement area of the connection assembly of the stator coil in a measurement range set in advance by a laser non-contact three-dimensional shape measurement device, second measuring a three-dimensional shape of a measurement area of the connection assembly of the stator coil in a measurement range set in advance by a multi-joint contact three-dimensional shape measurement device, the multi-joint contact three-dimensional shape measurement device including a plurality of arms being coupled via a joint including a built-in encoder, and integrally synthesizing the three-dimensional shape data measured in the first measurement, the three-dimensional shape data measured in the second measurement, and shape measurement data of a local area measured manually, thereby drafting a plan of the stator connection assembly. | 06-10-2010 |