Patent application number | Description | Published |
20110022646 | PROCESSOR, CONTROL METHOD OF PROCESSOR, AND COMPUTER READABLE STORAGE MEDIUM STORING PROCESSING PROGRAM - A processor for dividing by calculating repeatedly an n-bit width partial quotient includes, a dividend zero count value counter that counts a dividend zero count value, a divisor zero count value counter that counts a divisor zero count value, a correction value calculator that calculates a correction value to a loop count value, a correction loop count value calculator that calculates a correction loop count value, a dividend shift unit that shifts leftward an absolute value of the dividend by the dividend zero count value and shifts rightward the leftward-shifted absolute value of the dividend by the correction value, a divisor shift unit that shifts leftward an absolute value of the divisor by the divisor zero count value, and a division loop operation unit that divides based on an output value from the dividend shift unit, an output value from the divisor shift unit, and the correction loop count value. | 01-27-2011 |
20120254271 | ARITHMETIC OPERATION CIRCUIT AND METHOD OF CONVERTING BINARY NUMBER - An arithmetic operation circuit includes: an extractor circuit that extracts one or a plurality of bits consecutive from a most significant bit or from a least significant bit of a binary number; a sum register that stores an X-adic sum, where X is an integer more than two; and an update circuit that updates the stored X-adic sum with a value obtained by adding a first X-adic number to be cyclically multiplied by a certain coefficient to the X-adic sum in accordance with the extracted one or plurality of bits. | 10-04-2012 |
20120259903 | ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT - An arithmetic circuit for rounding pre-rounded data includes a first register to store first-format pre-rounded data that includes a mantissa of a fixed-precision floating-point number using a base-N numbering system, and includes an exponent for the mantissa, a second register to store rounding precision data indicative of precision for rounding the pre-rounded data, a leading zero counting unit to count consecutive zeros starting from a most significant bit of the mantissa stored in the first register, an exponent generating unit to generate a post-round exponent indicative of an exponent for a rounded significant by subtracting the number of zeros counted by the leading zero counting unit and the rounding precision data from a sum of one and the exponent stored in the first register, and an output register to store the post-round exponent and a rounding-add value that is to be added to a digit at which rounding is performed. | 10-11-2012 |
20120259905 | ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT - An arithmetic circuit for quantizing pre-quantized data includes a first input register to store first-format pre-quantized data that includes a mantissa and an exponent, a second input register to store a quantization target exponent, an exponent-correction-value indicating unit to indicate an exponent correction value, an exponent generating unit to generate a quantized exponent obtained by subtracting the exponent correction value from the quantization target exponent, a shift amount generating unit to generate a shift amount obtained by subtracting the exponent of the pre-quantized data and the exponent correction value from the quantization target exponent, a shift unit to generate a quantized mantissa obtained by shifting the mantissa of the pre-quantized data by the shift amount generated by the shift amount generating unit, and an output register to store quantized data that includes the quantized exponent generated by the exponent generating unit and the quantized mantissa generated by the shift unit. | 10-11-2012 |
20120259906 | ARITHMETIC CIRCUIT, ARITHMETIC PROCESSING APPARATUS AND METHOD OF CONTROLLING ARITHMETIC CIRCUIT - An arithmetic circuit calculates a correction value for a value that is obtained by an add-subtract operation of two values and that is expressed in a predetermined fixed precision. | 10-11-2012 |
20130073930 | PARITY PREDICTOR, CARRY-LESS MULTIPLIER AND ARITHMETIC OPERATION PROCESSING APPARATUS - A predictor configured to predict a parity value of a Carry-Less multiplication result of a multiplicand data string and a multiplier data string being two data strings in which q (q is a natural number) data units being p-bit (p is a natural number equal to two or above) data, includes a unit configured to predict a parity value of a first data unit from lower order in a result data string representing the multiplication result based on a value and a parity value of a first data unit from lower order in each of the two data strings; and a unit configured to predict a parity value for data at a high-order p−1 bit of the result data string based on a value and a parity value for a q-th data unit from lower order in each of the two data strings. | 03-21-2013 |
20140059096 | DIVIDING DEVICE AND DIVIDING METHOD - A dividing device includes: shifting circuits which left-shift the mantissa parts of the dividend and the divisor by a first and a second count values; a digit number arithmetic circuit which calculates a quotient digit number expected value based on the first count value and the second count value; a dividing circuit which outputs a quotient and a remainder in sequence on a digit-by-digit basis based on the mantissa parts of the dividend and the divisor left-shifted by the shifting circuits; a subtracting circuit which subtracts an exponent part of the floating-point number being the divisor from an exponent part of the floating-point number being the dividend to output a resultant value; and a control circuit which outputs a mantissa part and an exponent part of a floating-point number being a quotient. | 02-27-2014 |
20140059097 | MULTIPLYING DEVICE AND MULTIPLYING METHOD - A multiplying device includes: a circuit which left-shifts a mantissa part of a floating-point number being a multiplicand by a shift amount; a circuit which calculates a digit number of the mantissa part of the multiplier by subtracting the count value from the digit number of the fixed precision of the mantissa part; a multiplying circuit which outputs an intermediate product on a digit-by-digit basis of the mantissa part of the multiplier based on the mantissa part of the left-shifted multiplicand and the mantissa part of the multiplier; an adding circuit which adds exponent parts of the multiplicand and the multiplier; and a control circuit which outputs the intermediate product output by the multiplying circuit, as a mantissa part of a floating-point number being a product and outputs the value output by the adding circuit, as an exponent part of the floating-point number being the product. | 02-27-2014 |
20140059104 | ARITHMETIC CIRCUIT FOR CALCULATING CORRECTION VALUE - An arithmetic circuit for calculating a correction value for a result of an arithmetic operation that is an addition or subtraction performed with respect to a first floating-point number and a second floating-point number smaller than the first floating-point number. The arithmetic circuit includes a generation unit configured to generate a significand of a normalized correction value for the result of the arithmetic operation and an exponent of the normalized correction value based on the sign, the significand, and the exponent of the second floating-point number when a difference between a result of subtracting the leading zero count of the significand of the first floating-point number from the corresponding exponent and a result of subtracting a leading zero count of the significand of the second floating-point number from the corresponding exponent is larger than or equal to a second predetermined value. | 02-27-2014 |
20140059106 | ARITHMETIC CIRCUIT FOR PERFORMING DIVISION BASED ON RESTORING DIVISION - An arithmetic circuit for performing division based on restoring division includes an intermediate remainder register configured to store an intermediate remainder, a quotient prediction circuit configured to perform, based on information about two most significant digits of the intermediate remainder and a most significant digit of a divisor, quotient prediction having lower precision than a highest precision obtainable from the information, thereby generating a prediction result, a fixed-value multiplication circuit configured to output one or more N-th (N: integer) multiples of the divisor selected in response to the prediction result, one or more subtracters configured to subtract, from the intermediate remainder, the one or more N-th multiples of the divisor output from the fixed-value multiplication circuit, and a partial quotient calculating circuit configured to obtain a partial quotient in response to one or more carry-out bits of one or more subtractions performed by the one or more subtracters. | 02-27-2014 |