Patent application number | Description | Published |
20130256536 | METHODS AND SYSTEMS FOR DETERMINING TIMING RECOVERY INFORMATION IN A POSITRON EMISSION TOMOGRAPHY (PET) SYSTEM - A method and system for determining timing recovery information in a positron emission tomography (PET) system. One method includes determining energy information from pairs of light sensors of detectors of the TOF PET system, determining timing information from the pairs of light sensors of the detectors of the TOF PET system and calculating timing recovery information using the determined energy and timing information. | 10-03-2013 |
20130284936 | POSITRON EMISSION TOMOGRPAHY DETECTOR FOR DUAL-MODALITY IMAGING - A Positron Emission Tomography (PET) detector assembly includes a cold plate having a first side and an opposite second side, the cold plate being fabricated from a thermally conductive and electrically non-conductive material, a plurality of PET detector units coupled to the first side of the cold plate, and a readout electronics section coupled to the second side of the cold plate. A radio frequency (RF) body coil assembly and a dual-modality imaging system are also described herein. | 10-31-2013 |
20130327932 | METHODS AND SYSTEMS FOR GAIN CALIBRATION OF GAMMA RAY DETECTORS - Methods and systems for gain calibration of a gamma ray detector are provided. One method includes measuring signals generated by one or more light sensors of a gamma ray detector, generating one or more derived curves using the measured signals as a function of bias voltage and identifying a transition point in the one or more derived curves. The method also includes determining a breakdown voltage of the one or more light sensors using the identified transition point and setting a bias of the one or more light sensors based on the determined breakdown voltage. | 12-12-2013 |
20130334428 | METHODS AND SYSTEMS FOR SIGNAL COMMUNICATION IN GAMMA RAY DETECTORS - Methods and systems for signal communication in gamma ray detectors are provided. One gamma ray detector includes a scintillator block having a plurality of scintillator crystals and a plurality of light sensors coupled to the scintillator crystals and having a plurality of microcells. Each of the plurality of light sensors has a first set of signal traces connected to the microcells and a second set of signal traces connected along the first set of signal traces and together forming a signal path to a summing signal trace. Each of the plurality of light sensors also has a pin-out connected to the summing signal trace. | 12-19-2013 |
20150219771 | SYSTEMS AND METHODS FOR SCINTILLATORS HAVING POLISHED AND ROUGHENED SURFACES - A scintillator crystal array that is configured to receive rays emitted by an object to be imaged and to emit light energy responsive to the received rays includes plural crystals. At least one of the crystals includes an upper surface, a lower surface, and plural sides. The upper surface may be configured to receive the rays from the object to be imaged. The lower surface is disposed opposite the upper surface. The plural sides extend between the upper surface and the lower surface. At least one side includes a roughened side surface and at least one other side includes a polished side surface. | 08-06-2015 |
Patent application number | Description | Published |
20110201201 | METHODS OF FABRICATING LARGE-AREA, SEMICONDUCTING NANOPERFORATED GRAPHENE MATERIALS - Methods for forming a nanoperforated graphene material are provided. The methods comprise forming an etch mask defining a periodic array of holes over a graphene material and patterning the periodic array of holes into the graphene material. The etch mask comprises a pattern-defining block copolymer layer, and can optionally also comprise a wetting layer and a neutral layer. The nanoperforated graphene material can consist of a single sheet of graphene or a plurality of graphene sheets. | 08-18-2011 |
20120325405 | METHODS OF FABRICATING LARGE-AREA, SEMICONDUCTING NANOPERFORATED GRAPHENE MATERIALS - Methods for forming a nanoperforated graphene material are provided. The methods comprise forming an etch mask defining a periodic array of holes over a graphene material and patterning the periodic array of holes into the graphene material. The etch mask comprises a pattern-defining block copolymer layer, and can optionally also comprise a wetting layer and a neutral layer. The nanoperforated graphene material can consist of a single sheet of graphene or a plurality of graphene sheets. | 12-27-2012 |
20130108839 | NANOSTRUCTURED GRAPHENE WITH ATOMICALLY-SMOOTH EDGES | 05-02-2013 |
20130160701 | BARRIER GUIDED GROWTH OF MICROSTRUCTURED AND NANOSTRUCTURED GRAPHENE AND GRAPHITE - Methods for growing microstructured and nanostructured graphene by growing the microstructured and nanostructured graphene from the bottom-up directly in the desired pattern are provided. The graphene structures can be grown via chemical vapor deposition (CVD) on substrates that are partially covered by a patterned graphene growth barrier which guides the growth of the graphene. | 06-27-2013 |
20140235755 | INIMER-CONTAINING RANDOM COPOLYMERS AND CROSSLINKED COPOLYMER FILMS FOR DENSE POLYMER BRUSH GROWTH - Crosslinkable random copolymers comprising atom transfer radical polymerization (ATRP) initiators and crosslinked copolymer films formed from the copolymers are provided. The random copolymers, which are polymerized from one or more alkyl halide functional inimers and one or more monomers having a crosslinkable functionality, are characterized by pendant ATRP initiating groups and pendant crosslinkable groups. | 08-21-2014 |
20140263164 | DEGRADABLE NEUTRAL LAYERS FOR BLOCK COPOLYMER LITHOGRAPHY APPLICATIONS - Polymer films comprising crosslinked random copolymers and methods for making the films are provided. Also provided are polymer films comprising random copolymers that are covalently linked to an underlying substrate. The polymer films can be incorporated into structures in which the films are employed as surface-modifying layers for domain-forming block copolymers and the structures can be used for pattern transfer applications via block copolymer lithography. The crosslinks between the random copolymer chains in the polymer films or the links between the random copolymer chains and the substrate surface are characterized in that they can be cleaved under relatively mild conditions. | 09-18-2014 |
20140263175 | CROSSLINKED RANDOM COPOLYMER FILMS FOR BLOCK COPOLYMER DOMAIN ORIENTATION - Surface-modifying layers, including neutral layers for vertical domain-forming block copolymers of styrene and methyl methacrylate are provided. Also provided are self-assembled block copolymer structures incorporating the surface modifying layers, methods of fabricating such structures and methods of using the structures in BCP lithography applications. The surface-modifying layers comprise a crosslinked copolymer film, wherein the crosslinked copolymers are random copolymers polymerized from styrene monomers and/or (meth)acrylate monomers and crosslinkable epoxy group-functionalized monomers. The crosslinked copolymer films are characterized by a high content of the crosslinkable epoxy group-functionalized monomer. | 09-18-2014 |
20140272673 | BLOCK COPOLYMER-BASED MASK STRUCTURES FOR THE GROWTH OF NANOPATTERNED POLYMER BRUSHES - Block copolymer-based mask structures for the growth of patterned polymer brushes via surface-initiated atom transfer radical polymerization (SI-ATRP) are provided. Also provided are methods of making the mask structures and methods of using the mask structures to grow patterned polymer brushes. The mask structures comprise a substrate having a surface, a neutral layer comprising a crosslinked copolymer film disposed on the surface of the substrate and a domain-forming block copolymer film disposed on the crosslinked copolymer film. The crosslinked copolymer film comprises crosslinked random copolymer chains having pendant alkyl halide functional groups that are capable of acting as ATRP initiating sites. | 09-18-2014 |
20140273361 | METHODS FOR THE FABRICATION OF GRAPHENE NANORIBBON ARRAYS USING BLOCK COPOLYMER LITHOGRAPHY - Methods of fabricating patterned substrates, including patterned graphene substrates, using etch masks formed from self-assembled block copolymer films are provided. Some embodiments of the methods are based on block copolymer (BCP) lithography in combination with graphoepitaxy. Some embodiments of the methods are based on BCP lithography techniques that utilize hybrid organic/inorganic etch masks derived from BCP templates. Also provided are field effect transistors incorporating graphene nanoribbon arrays as the conducting channel and methods for fabricating such transistors. | 09-18-2014 |
20150099109 | BLOCK COPOLYMERS WITH HIGH FLORY-HUGGINS INTERACTION PARAMETERS FOR BLOCK COPOLYMER LITHOGRAPHY - Block copolymers for use in block copolymer lithography, self-assembled films of the block copolymers and methods for polymerizing the block copolymers are provided. The block copolymers are characterized by high Flory-Huggins interaction parameters (χ). The block copolymers can be polymerized from protected hydroxystyrene monomers or from tert-butyl styrene and 2-vinylpyridine monomers. | 04-09-2015 |
Patent application number | Description | Published |
20120042176 | Method and Apparatus for Optimizing Clock Speed and Power Dissipation in Multicore Architectures - A multicore processor provides for local power control at each of the cores which is used to lower the maximum operating frequency of cores by any amount above of the maximum operating frequency of the slowest core. This power savings is then used to increase the maximum operating frequency of the frequency balanced cores within a power constraint. | 02-16-2012 |
20140047199 | Memory-Link Compression for Graphic Processor Unit - A graphic processing unit having multiple computational elements flexibly interconnected to memory elements provides for data compressors/decompressors in the memory channels communicating between the computational elements and memory elements to provide an effective increase in bandwidth of those connections by the compression of data transferred thereon. | 02-13-2014 |
20140068304 | METHOD AND APPARATUS FOR POWER REDUCTION DURING LANE DIVERGENCE - A method and device for reducing power during an instruction lane divergence includes idling an inactive execution lane during the lane divergence. | 03-06-2014 |
20140280430 | Multiplier Circuit with Dynamic Energy Consumption Adjustment - A fixed point multiplier that can be used in mobile computer systems operating under limited power constraints provides a trade-off between computational accuracy and energy consumption that may be changed dynamically for energy conservation purposes. In one embodiment, the multiplier pre-stores multiplication shift coefficients to eliminate leading-one circuitry normally used in shift and accumulate multipliers. | 09-18-2014 |
20140325248 | APPARATUS AND METHOD FOR ADJUSTING BANDWIDTH - A method for adjusting bandwidth, a bandwidth scaler and an apparatus are provided. The method for adjusting bandwidth involves determining a dynamic context of a processor, and based on the determined dynamic context, scaling bandwidth between the processor and a memory. | 10-30-2014 |
20140337853 | Resource And Core Scaling For Improving Performance Of Power-Constrained Multi-Core Processors - A multi-core processor provides circuitry for jointly scaling the number of operating cores and the amount of resources per core in order to maximize processing performance in a power-constrained environment. Such scaling is advantageously provided without the need for scaling voltage and frequency. Selection of the number of operating cores and the amount of resources per core is made by examining the degree of instruction and thread level parallelism available for a given application. Accordingly, performance counters (and other characteristics) implemented in by a processor may be sampled on-line (in real time) and/or performance counters for a given application may be profiled and characterized off-line. As a result, improved processing performance may be achieved despite decreases in core operating voltages and increases in technology process variability over time. | 11-13-2014 |
20150113304 | ENERGY-EFFICIENT MULTICORE PROCESSOR ARCHITECTURE FOR PARALLEL PROCESSING - A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption. | 04-23-2015 |
20150128007 | Dynamic Error Handling For On-Chip Memory Structures - A memory structure is provided that controls the activation of error handling bits as a function of operating voltage. In this way, error correction can be used to offset errors when the memory structure is run at low voltage (and frequency). However, negative performance impacts for such error correction, such as additional access latencies, can be avoided when the memory structure is run at higher voltage (and frequency) and memory errors are less likely. In addition, increased latencies due to evaluating error handling bits may be hidden by reading digital data bits from the memory structures speculatively and assuming no errors. Also, certain portions of memory structures may have larger cells, and therefore larger areas, than other portions, which may provide not only higher reliability at low operating voltages, but also faster operation with reduced latency. | 05-07-2015 |
20150234693 | Method and Apparatus for Soft Error Mitigation in Computers - Hardening of an integrated circuit such as a GPU processor to soft errors caused by particle strikes is applied selectively to the set of devices according to the magnitude of error resulting from this soft error for the particular device. This approach differs from approaches that protect all devices, all devices likely to produce an output error, or all devices that are vulnerable. | 08-20-2015 |
20150317277 | COMPUTER ARCHITECTURE HAVING SELECTABLE, PARALLEL AND SERIAL COMMUNICATION CHANNELS BETWEEN PROCESSORS AND MEMORY - A computer architecture provides both a parallel memory bus and serial memory bus between a processor system and memory. Latency-tolerant memory access requests are steered to the serial memory bus which operates to increase the available memory bus bandwidth on the parallel memory. The invention also provides integrated circuit computer memory suitable for this application. | 11-05-2015 |
20150370537 | High Efficiency Computer Floating Point Multiplier Unit - A high-power-efficiency multiplier combines a standard floating-point multiplier with a power-of-two multiplier that performs multiplications by shifting operations without the need for floating-point multiplication circuitry. By selectively steering some operands to this power-of-two multiplier, substantial power savings may be realized. In one embodiment, multiplicands may be modified to work with the power-of-two multiplier introducing low errors that may be accommodated in pixel calculations. | 12-24-2015 |
20160041813 | Multiplication Circuit Providing Dynamic Truncation - A fixed-point multiplier providing reduced energy usage dynamically truncates received operands according to the location of computationally important bits in the operands and provides the truncated operands to a reduced width multiplier offering reduced energy usage. Information about the location of the dynamic truncation is used to properly shift the result of the multiplier to provide an approximation of full multiplication of the operands. | 02-11-2016 |
20160048188 | Voltage Regulator Control for Improved Computing Power Efficiency - A controller for voltage regulators providing power to computer processors may control the number of active phases of each voltage regulator according to a determined electrical current demand from the processor. By relying on electrical current demand rather than a P-state, the latter generally indicating a power conservation status, improved regulator efficiencies may be had, in particular responding to situations where low current demand occurs under heavy processor demand because of C-state variations. | 02-18-2016 |
20160054932 | Memory Controller for Heterogeneous Computer - A memory controller for heterogeneous computer processors dynamically adjusts access priorities by the different processors to maximize performance in the execution of a single parallel application program on both processor architectures. In one embodiment, the memory controller predicts sequential memory accesses by the processor having higher memory latency or fewer access requests to lockout the other processor during those sequences for improved implementation of the intended prioritization. | 02-25-2016 |
20160103729 | Memory Fault Patching Using Pre-Existing Memory Structures - A computer architecture addresses intermittent memory faults by exploiting redundancy inherent in a hierarchical memory structure, for example, as data moves through various cache levels and registers before use by the processor. Accesses to data from faulted memory areas is diverted to a secondary memory structure holding that data and the secondary memory structure is flagged to increase the persistence of the stored data used for patching against normal updating policies. | 04-14-2016 |
Patent application number | Description | Published |
20080282455 | FLAME RESISTANT AND HEAT PROTECTIVE FLEXIBLE MATERIAL WITH INTUMESCING GUARD PLATES AND METHOD OF MAKING THE SAME - A protective material comprising a flexible substrate including a top surface and a plurality of discrete guard plates affixed to the top surface in a spaced relationship to each other. The guard plates comprise a material which significantly expands upon the addition of sufficient heat forming a thermally insulating, flame retardant layer. | 11-20-2008 |
20090142535 | SUPPLE PENETRATION RESISTANT FABRIC AND METHOD OF MAKING - A puncture, pierce, and cut resistant fabric comprised of a plurality of sheets of plates arranged in a repeating pattern. A material interconnects the plates. The fabric is twistable, bendable, and flexible. It is constructed of substances that will withstand cutting, puncture, and piercing forces encountered in medical or other environments. | 06-04-2009 |
20100158697 | MULTI-ROTOR VERTICAL AXIS WIND TURBINE - New aerodynamically improved rotors for use in vertical axis wind turbine (VAWTs) are disclosed. In some examples, the VAWT rotors include one or more blades with an aerodynamic front shape with low drag coefficient and a blunt or concave back shape that effectively catches the wind. Example rotors can be used by themselves or in conjunction with vertically attached rotating airfoils. The new rotors add to the overall energy production while acting as supports for the vertical airfoils. Furthermore, the new rotors provide energy in low wind speed conditions where the vertical airfoils are ineffective and can act as jump starters for the vertical airfoils. Guy wire structures for stabilizing VAWTs are also disclosed. The structures allow for reduced construction costs for a given tower height compared to conventional HAWTs and allows for taller towers for a given construction cost. The overall stability under wind gusts is improved by the guy wire design | 06-24-2010 |
20110168003 | ARMOR ASSEMBLY INCLUDING MULTIPLE ARMOR PLATES - In some example, the disclosure provides armor assembly designs utilizing multiple solid armor plates and one or more coupling elements, such as, e.g., high-strength ropes, to couple the solid armor plates to each other. For example, the solid armor plates may be attached to one another and held in position via high-strength ropes for form a discontinuous armor layer. The armor assemblies may include multiple layer arrangements of the solid armor plates that provide substantially complete coverage of a surface when the multiple discontinuous layers are combined. Ropes or other coupling elements may be used to horizontally connect plates together within the same discontinuous layer of armor plates and ropes may also be used to vertically connect plates in different armor layers. In some example, the armor assembly may be highly flexible and breathable to provide body armor that may be comfortably worn. In some examples, armor assemblies may be adapted for use as vehicle armor or other armor applications. | 07-14-2011 |
20130209735 | PROTECTIVE MATERIAL HAVING GUARD PLATES WITH IMPROVED SURFACE PROPERTIES - In some examples, the disclosure relates to a fabric assembly comprising a flexible substrate including a top surface; a plurality of plates affixed to the top surface of the flexible substrate and arrayed in a pattern such that a plurality of continuous gaps are defined between adjacent plates; and a coating formed on at least one of the substrate and plurality of guard plates, wherein the coating is selected to increase at least one of scuff resistance, oil resistance, water resistance, stain resistance of the fabric assembly. | 08-15-2013 |