Kim, Ichon-Si
Byoung Young Kim, Ichon-Si KR
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20120155190 | PAGE BUFFER CIRCUIT - A page buffer circuit includes: a main latch unit configured to have a main latch value which is dependent on a sub latch output signal, and output the main latch value to a first node; a sub latch unit configured to latch a voltage of a second node as a sub latch value in response to a storage enable signal, and generate the sub latch output signal according to the sub latch value when an output enable signal is activated; and a voltage determination unit connected between the first node and the second node, and configured to electrically connect or disconnect the first node to or from the second node in response to the storage enable signal, and determine a voltage level of the second node in response to the storage enable signal. | 06-21-2012 |
Chulsik Kim, Ichon-Si KR
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20100203683 | SEMICONDUCTOR SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURE THEREOF - A method for manufacturing a semiconductor package system includes: providing a die having a plurality of contact pads; forming a leadframe having a plurality of lead fingers with flat tops of predetermined lengths, the plurality of lead fingers having a fine pitch and each having a trapezoidal cross-section; attaching a plurality of bumps to the plurality of lead fingers, the plurality of bumps on the tops, extending beyond the widths of the trapezoidal cross-sections, and clamping down on the two sides of each of the plurality of lead fingers; attaching a plurality of bond wires to the plurality of contact pads; attaching the plurality of bond wires to the plurality of bumps; and forming an encapsulant over the plurality of lead fingers, the die, and the plurality of bond wires, the encapsulant leaving lower surfaces of the plurality of lead fingers exposed. | 08-12-2010 |
20110169149 | SEMICONDUCTOR PACKAGE SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURING THEREOF - A semiconductor package system, and method of manufacturing thereof, includes: a die having a contact pad; a lead finger having a substantially trapezoidal cross-section; a bump clamped on a top and a side of the lead finger, the bump connected to the contact pad; and an encapsulant over the lead finger and the die, the encapsulant with a bottom of the lead finger exposed. | 07-14-2011 |
20110285000 | SEMICONDUCTOR SYSTEM WITH FINE PITCH LEAD FINGERS AND METHOD OF MANUFACTURING THEREOF - A semiconductor package system, and method of manufacturing thereof, includes: an electrical substrate having a contact pad; a support structure having a lead finger thereon; a bump on the lead finger, the bump clamped on a top and a side of the lead finger and connected with the contact pad; and an encapsulant over the lead finger and the electrical substrate. | 11-24-2011 |
Chul-Sik Kim, Ichon-Si KR
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20100225008 | WIRE BOND INTERCONNECTION - A wire bond interconnection between a die pad and a bond finger includes a support pedestal at a bond site of the lead finger, a ball bond on the die pad, and a stitch bond on the support pedestal, in which a width of the lead finger at the bond site is less than a diameter of the support pedestal. Also, a semiconductor package including a die mounted onto and electrically connected by a plurality of wire bonds to a substrate, in which each of the wire bonds includes a wire ball bonded to a pad on the die and stitch bonded to a support pedestal on a bond site on a lead finger, and in which the width of the lead finger at the bond site is less than the diameter of the support pedestal. | 09-09-2010 |
20110266700 | WIRE BOND INTERCONNECTION AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal. | 11-03-2011 |
Dae Suk Kim, Ichon-Si KR
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20110128800 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: an address pad; an address pad buffer section configured to selectively receive a signal of the address pad; a data input buffer section configured to selectively receive the signal of the address pad; and a signal control section configured to selectively provide a path of the signal of the address pad to the address buffer section and the data input buffer section. | 06-02-2011 |
Dong Keun Kim, Ichon-Si KR
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20100302841 | PHASE CHANGE MEMORY APPARATUS AND TEST CIRCUIT THEREFOR - A test circuit transfers data, which is generated by current supplied from an external source, to a memory cell in response to a test mode signal. | 12-02-2010 |
20110075474 | PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS AND WRITE CONTROL METHOD FOR THE SAME - The disclosed phase change random access memory apparatus is configured to program a predetermined phase change memory cell in the phase change memory apparatus in response to a plurality of write instructions applied at independent points of time. | 03-31-2011 |
Guk Cheon Kim, Ichon-Si KR
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20130032910 | MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetic memory device includes a first fixing layer, a first tunnel barrier coupled to the first fixing layer, a free layer coupled to the first tunnel barrier and having a stacked structure including a first ferromagnetic layer, an oxide tunnel spacer, and a second ferromagnetic layer, a second tunnel barrier coupled to the free layer, and a second fixing layer coupled to the second tunnel barrier. | 02-07-2013 |
Gwang Kim, Ichon-Si KR
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20110215456 | THIN PACKAGE SYSTEM WITH EXTERNAL TERMINALS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a thin package system with external terminals includes: providing a leadframe; providing a template for defining an external bond finger; forming external bond fingers in the template on the leadframe; forming land pad terminals by a first multi-layer plating; providing a die; attaching the die to the land pad terminals above the leadframe with an adhesive on the leadframe; covering an encapsulant over at least portions of the die and the external bond fingers; and removing the leadframe leaving a surface of the adhesive coplanar with a surface of the encapsulant. | 09-08-2011 |
Gyung Tae Kim, Ichon-Si KR
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20110075498 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD USING THE SAME - A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense amplifier driving control unit configured to generate a first voltage supply control signal, a second voltage supply control signal and a third voltage supply control signal in response to the test signal, a sense amplifier enable test signal, a first voltage supply signal, a second voltage supply signal and a third voltage supply signal; and a voltage supply unit configured to provide the core voltage, an external voltage and a ground voltage to a sense amplifier with an open bit line structure in response to the first to third voltage supply control signals. | 03-31-2011 |
Hyoung-Joon Kim, Ichon-Si KR
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20090302294 | MULTI-BIT PHASE-CHANGE MEMORY DEVICE - A multi-bit phase-change memory device includes a semiconductor substrate with a plurality of phase-change patterns sequentially stacked above the semiconductor substrate. Each phase-change pattern crosses another phase change pattern, and each phase change pattern includes a phase-change conductive line formed on a surface thereof. Bipolar transistors are installed between the semiconductor substrate and the lowermost phase-change pattern and also among the phase-change patterns, and the bipolar transistors selectively form electrical connections between the semiconductor substrate and the lowermost phase-change pattern and also among the phase-change patterns. Heating electrodes are aligned between the respective bipolar transistors and phase-change patterns. The semiconductor substrate includes an active area that extends in a direction that is perpendicular to the extension direction of the lowermost phase-change pattern. | 12-10-2009 |
Hyung Soo Kim, Ichon-Si KR
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20100064163 | DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal. | 03-11-2010 |
20100117702 | DUTY CYCLE CORRECTION APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal. | 05-13-2010 |
Hyun Joung Kim, Ichon-Si KR
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20090256267 | INTEGRATED CIRCUIT PACKAGE-ON-PACKAGE SYSTEM WITH CENTRAL BOND WIRES - An integrated circuit package-on-package system includes: providing a base substrate having a central opening; attaching a bottom die below the base substrate partially covering the central opening, the bottom die connected through the central opening to a top surface of the base substrate; attaching a top die above the base substrate partially covering the central opening; attaching external conductive interconnections to a base bottom surface of the base substrate; and molding an encapsulant leaving the external conductive interconnections partially exposed. | 10-15-2009 |
20100237488 | INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING - A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts; attaching an integrated circuit to the top surface; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that are over and larger than the electrical contacts. | 09-23-2010 |
Jae Yun Kim, Ichon-Si KR
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20120081961 | NONVOLATILE MEMORY APPARATUS CAPABLE OF REDUCING CURRENT CONSUMPTION AND RELATED DRIVING METHOD - Various exemplary embodiments of a nonvolatile memory apparatus are disclosed. In one exemplary embodiment, the memory apparatus may include: a page buffer; an even bit line connected to the page buffer; an odd bit line connected to the page buffer; an even memory cell string installed on the even bit line; an dd memory cell string installed on the odd bit line; and a bit line select unit configured to selectively generate a signal read path between the even bit line and the even memory cell string or between the odd bit line and the odd memory cell string. | 04-05-2012 |
Jee Yul Kim, Ichon-Si KR
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20110148444 | CIRCUIT FOR TESTING INTERNAL VOLTAGE OF SEMICONDUCTOR MEMORY APPARATUS - An internal voltage test circuit of a semiconductor memory apparatus includes a comparing unit for comparing a level of internal voltage with a level of external voltage to output a comparison result as an output signal during a test mode, and an output selecting unit for outputting the output signal to a data output pad during the test mode, and outputting a data signal to the data output pad during a normal operation mode. | 06-23-2011 |
Jin Chul Kim, Ichon-Si KR
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20100232226 | SOLID STATE STORAGE SYSTEM FOR UNIFORMLY USING MEMORY AREA AND METHOD CONTROLLING THE SAME - A solid state storage system includes a memory area having a plurality of pages and is capable of storing program information about each page. The memory area stores the number of pulse counts applied to each page. A main memory controller receives the program information from the memory area and determines whether to program pages according to the program information. The main memory controller determines whether the program information for a page is at a predetermined amount and if the corresponding page should be programmed again or not. | 09-16-2010 |
Jong Su Kim, Ichon-Si KR
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20110266597 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an isolation layer formed on a semiconductor substrate; an active region defined by the isolation layer; at least one gate line formed to overlap with the active region; at least one first active tab formed on a first interface of the active region which overlaps with the gate line; and a first gate tab formed on a second interface facing away from the first interface in such a way as to project from the gate line. | 11-03-2011 |
20130043925 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING VOLTAGE STABILIZING CIRCUIT - A semiconductor integrated circuit includes a first voltage supply unit, a second voltage supply unit configured to supply a voltage with a level different from that of the first voltage supply unit, and a voltage stabilizing unit connected between the first and second voltage supply units, and including at least one discharge path that includes a clamping section configured to temporarily drop a level of a voltage introduced from the first or second voltage supply unit, and a discharge section configured to discharge the voltage having passed through the clamping section to the second or first voltage supply unit. | 02-21-2013 |
20130309836 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes an isolation layer formed on a semiconductor substrate; an active region defined by the isolation layer; at least one gate line formed to overlap with the active region; at least one first active tab formed on a first interface of the active region which overlaps with the gate line; and a first gate tab formed on a second interface facing away from the first interface in such a way as to project from the gate line. | 11-21-2013 |
Ki Han Kim, Ichon-Si KR
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20100289542 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock. | 11-18-2010 |
20110025384 | DEVICE FOR GENERATING CLOCK IN SEMICONDUCTOR INTEGRATED CIRCUIT - Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port. | 02-03-2011 |
Ki Up Kim, Ichon-Si KR
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20100164541 | TERMINATION CONTROL CIRCUIT AND METHOD FOR GLOBAL INPUT/OUTPUT LINE - A termination control circuit for a global input/output line includes a speed determination unit configured to output a termination enable signal which is activated in response to a frequency of an external clock signal and CAS latency information; and a pulse generation unit configured to output a driving signal for driving a termination circuit for the global input/output line in response to a termination control signal and the termination enable signal. | 07-01-2010 |
Kwan Dong Kim, Ichon-Si KR
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20090278580 | CLOCK CONTROL CIRCUIT AND A SEMICONDUCTOR MEMORY APPARATUS HAVING THE SAME - A clock control circuit includes a clock delay device, an edge detection device, a phase determination device and a delay control device. The clock delay device generates a delayed rising clock and a delayed falling clock by delaying a rising clock and a falling clock, which are transferred from a clock generation circuit, in response to a control signal, and to transfer the delayed rising clock and the delayed falling clock to a data output buffer. The edge detection device detects a difference between an edge timing of the delayed rising clock and an edge timing of the delayed falling clock to generate edge detection signals. The phase determination device detects a duty ratio of each of the edge detection signals to generate phase determination signals. The delay control device generates the control signal in response to the phase determination signals. | 11-12-2009 |
20100091592 | CLOCK BUFFER AND A SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after a clock enable signal is enabled, a delay enable signal generator configured to generate a delayed enable signal enabled in synchronization with a rising edge of a second period of a first clock after the reference enable signal is enabled, a first output unit configured to receive the reference enable signal and the first clock to generate a first internal clock, and a second output unit configured to receive the delayed enable signal and the second clock to generate a second internal clock. | 04-15-2010 |
Kyeong Rho Kim, Ichon-Si KR
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20110161727 | SOLID STATE STORAGE SYSTEM FOR CONTROLLING RESERVED AREA AND METHOD OF CONTROLLING THE SAME - A solid state storage system includes a flash memory region comprising a plurality of memory blocks and a plurality of replacement blocks corresponding to error-occurred blocks when errors occur in the memory blocks; and a memory controller configured to perform a control operation to replace the error-occurred blocks with the replacement blocks, wherein the error-occurred blocks comprise correctable blocks and uncorrectable blocks, and wherein the memory controller determines whether the error-occurred blocks are the correctable blocks or the uncorrectable blocks and controls zones of the replacement blocks, replaced in correspondence to the correctable blocks, to be allocated a plurality of times. | 06-30-2011 |
20120159280 | METHOD FOR CONTROLLING NONVOLATILE MEMORY APPARATUS - There is provided a method for controlling a nonvolatile memory apparatus in a nonvolatile memory system including a host interface, a memory controller, and a memory area. The method includes: checking a number of ECC fail bits, determining whether or not to replace a corresponding block, and replacing the block, while a read command provided from the host interface is performed; and replacing a block, which was not replaced during the read operation, with a block to be used as a replacement target during a write operation. | 06-21-2012 |
20120191897 | NON-VOLATILE MEMORY SYSTEM AND MANAGEMENT METHOD THEREOF - A non-volatile memory system includes a memory area including a plurality of non-volatile memory blocks, and a micro control unit configured to manage the memory blocks as a data block and a buffer block. As a write command is input, if no buffer block assigned to the data block exists and a free page exists in the data block, the micro control unit converts the data block to a self-buffer block. | 07-26-2012 |
Kyungeun Kim, Ichon-Si KR
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20130154078 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH HEAT SLUG AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation. | 06-20-2013 |
Kyung-Moon Kim, Ichon-Si KR
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20090045507 | Flip chip interconnection - Methods for forming flip chip interconnection, in which the bump interconnect is defined at least in part by an underfill. The underfill includes a material that is thermally cured; that is, raising the temperature of the underfill material can result in progressive curing of the underfill through stages including a gel stage and a fully cured stage. According to the invention, during at least an early stage in the process the semiconductor chip is carried by a thermode, which is employed to control the temperature of the assembly in a specified way. Also, flip chip interconnections and flip chip packages made according to the methods of invention. | 02-19-2009 |
Kyu Sung Kim, Ichon-Si KR
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20130103883 | NONVOLATILE MEMORY APPARATUS AND WRITE CONTROL METHOD THEREOF - A nonvolatile memory apparatus includes a memory cell array, and a write operation controller configured to verify a write operation by comparing input data to the write operation controller with cell data written into the memory cell array, measure a resistance value after a first time is elapsed, and determine whether or not to re-perform the write operation according to the measured resistance value. | 04-25-2013 |
Min Su Kim, Ichon-Si KR
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20120198180 | NONVOLATILE MEMORY SYSTEM AND FLAG DATA INPUT/OUTPUT METHOD FOR THE SAME - Various embodiments of a nonvolatile memory system and related methods are disclosed. In one exemplary embodiment, the memory system may include: a memory area including a main memory area and a flag memory area; and an input/output controller configured to receive main data through a main data input line and provide the received main data to a page buffer circuit in response to a main data input control signal. The input/output controller may be further configured to receive flag data through the main data input line and provide the received flag data to the page buffer circuit in response to a flag data input control signal. | 08-02-2012 |
Myoung Sub Kim, Ichon-Si KR
Oh Han Kim, Ichon-Si KR
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20080303142 | ELECTRONIC SYSTEM WITH VERTICAL INTERMETALLIC COMPOUND - An electronic system is provided including forming a substrate having a contact, forming a conductive structure over the contact, mounting an electrical device having an external interconnect over the conductive structure, and forming a conductive protrusion from the conductive structure in the external interconnect. | 12-11-2008 |
20110316162 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH TRENCHES AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate with a material layer including grooves in a fillet region that are substantially parallel and adjacent an integrated circuit; and forming a resin between the substrate and the integrated circuit that contacts a trench trace exposed by the grooves. | 12-29-2011 |
20120068319 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACK INTERCONNECT AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: forming a connection carrier having base device pads and base interconnect pads on a carrier top side of the connection carrier; connecting a base integrated circuit to the base device pads and mounted over the carrier top side; mounting base vertical interconnects directly on the base interconnect pads; attaching a base package substrate to the base integrated circuit and directly on the base vertical interconnects; forming a base encapsulation on the base package substrate, the base device pads, and the base interconnect pads; and removing a portion of the connection carrier with the base device pads and the base interconnect pads partially exposed opposite the base package substrate. | 03-22-2012 |
20120319300 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate with a projection formed along a perimeter of a first surface of the substrate; mounting an integrated circuit over the first surface; forming a protruding interconnect over the first surface between the projection and the integrated circuit; and forming an underfill between the integrated circuit and the projection with a uniform height, the uniform height of the underfill less than a height of the projection. | 12-20-2012 |
20120326291 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching a flip chip to the substrate; attaching a heat slug to the substrate and the flip chip; and forming a moldable underfill having a top underfill surface on the substrate, the flip chip, and the heat slug, the moldable underfill having a characteristic of being liquid at room temperature and the top underfill surface over the flip chip. | 12-27-2012 |
20130069224 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE UNDERLAYER AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a routable layer having a column; mounting an integrated circuit structure in direct contact with the column; and forming a gamma connector to electrically connect the column to the integrated circuit structure. | 03-21-2013 |
20130154079 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE MOLD GATE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a mold gate on an upper surface of the substrate; mounting an integrated circuit to the substrate; and forming an encapsulant encapsulating the integrated circuit, the encapsulant having disruption patterns emanating from the mold gate and underneath a bottom plane of the integrated circuit. | 06-20-2013 |
Sang Hui Kim, Ichon-Si KR
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20120176853 | REFRESH CONTROL CIRCUIT, MEMORY APPARATUS AND REFRESH CONTROL METHOD USING THE SAME - A memory apparatus is configured to generate refresh addresses with different values in response to one refresh command and an address, and perform a plurality of refresh operations with time differences in response to the refresh addresses. Herein, the refresh operations are performed within a refresh row cycle time. | 07-12-2012 |
Sang-Hyun Kim, Ichon-Si KR
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20100021258 | AIR ROLL UNIT FOR CONTAINER CAR - The present invention relates to an air roll unit for container car, and more particularly to, a container car, characterized in comprising: a main frame having a rail formed by longitudinal direction, and a joint formed on both sides; a tube inserted into the rail of the main frame with an air nozzle on both ends; a roll plate fixed on the top of the tube; and a connection frame pressedly fixed to the rail of the main frame neighbored and combined into one end of the roll plate. According to the present invention as above, manufacturing costs and terms can be relatively reduced by enabling to unify a baseplate and a roll plate and extend the adjoining baseplate and roll plate. | 01-28-2010 |
Sang Sik Kim, Ichon-Si KR
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20120185654 | SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING RANDOM CODE GENERATION CIRCUIT, AND DATA PROGRAMMING METHOD - A semiconductor apparatus includes a plurality of linear feedback shift registers configured to receive a plurality of seed codes as initial values and generate respective random codes under a control of a clock signal, a code combination section configured to logically combine the plurality of random codes generated by the plurality of linear feedback shift registers and generate a final random code, and a data conversion unit configured to convert input data based on the final random code and output conversion data. | 07-19-2012 |
Seung Bong Kim, Ichon-Si KR
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20100128540 | SEMICONDUCTOR MEMORY APPARATUS AND TEST CIRCUIT THEREFOR - A test circuit for a semiconductor memory apparatus of an open bit-line structure includes a compression part configured to, in response to test data read from a plurality of memory cells included in a test target cell mat and a compression control signal generated from a compression control signal generating part, compress the test data that are read from the memory cells that share a sense amplifier block and sequentially output compression test signals. | 05-27-2010 |
Soo Gil Kim, Ichon-Si KR
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20120057402 | WRITE DRIVER, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME AND PROGRAMMING METHOD - A write driver, a semiconductor memory apparatus using the same, and a programming method. The write driver includes a reset control unit configured to output a first current pulse for a first period of time and subsequently output a second current pulse having a higher current level than the first current pulse for a second period of time to a memory cell array in response to a reset program command. | 03-08-2012 |
20130016555 | SEMICONDUCTOR INTERGRATED CIRCUIT DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAMEAANM KIM; Myoung SubAACI Ichon-siAACO KRAAGP KIM; Myoung Sub Ichon-si KRAANM Kim; Soo GilAACI Ichon-siAACO KRAAGP Kim; Soo Gil Ichon-si KRAANM Park; Nam KyunAACI Ichon-siAACO KRAAGP Park; Nam Kyun Ichon-si KRAANM Kim; Sung CheoulAACI Ichon-siAACO KRAAGP Kim; Sung Cheoul Ichon-si KRAANM Do; Gap SokAACI Ichon-siAACO KRAAGP Do; Gap Sok Ichon-si KRAANM Sim; Joon SeopAACI Ichon-siAACO KRAAGP Sim; Joon Seop Ichon-si KRAANM Lee; Hyun JeongAACI Ichon-siAACO KRAAGP Lee; Hyun Jeong Ichon-si KR - A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode. | 01-17-2013 |
20130033919 | NONVOLATILE MEMORY SYSTEM AND PROGRAM METHOD THEREOF - A nonvolatile memory system and a program method thereof are provided. The nonvolatile memory system includes a nonvolatile memory cell array, an input/output (I/O) control circuit configured to control a program or read operation for the nonvolatile memory cell array; and a controller configured to store an equation representing a resistance-current (R-I) curve for resistance states of memory cells included in the nonvolatile memory cell array, apply an initial program current calculated based on the equation, calculate the equation based in on a resistance of a memory cell subjected to the initial program current, predict a reprogram current based on the equation obtained from the calculation, and control the I/O control circuit. | 02-07-2013 |
20130077392 | SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area. | 03-28-2013 |
Sung Cheol Kim, Ichon-Si KR
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20130103892 | COMBINED MEMORY BLOCK AND DATA PROCESSING SYSTEM HAVING THE SAME - A combined memory block includes a first memory unit configured to store data and an additional memory unit that forms a stacked structure with the memory unit, wherein the memory unit and the storage unit together form multi-level cells having variable resistance in storing data. | 04-25-2013 |
Sung Cheoul Kim, Ichon-Si KR
Yong Hoon Kim, Ichon-Si KR
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20120194244 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD FOR CORRECTING DUTY THEREOF - A semiconductor memory apparatus may comprise a duty cycle correction circuit configured to perform a duty correction operation with respect to an input clock signal when a delay locked signal is activated, and perform the duty correction operation with respect to the input signal when a precharge signal is activated, to generate a corrected clock signal. | 08-02-2012 |
Yong Ju Kim, Ichon-Si KR
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20090257537 | DATA RECOVERY CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS THAT MINIMIZES JITTER DURING DATA TRANSMISSION - A data recovery circuit that minimizes jitter during data transmission is presented. The data recovery circuit includes a data dividing unit, a data sampling unit, a data selecting unit, and a data recovery unit. The data dividing unit is for dividing external data to generate multiple-division data. The data sampling unit is for sampling the multiple-division data at a first time and a second time to generate sampling data. The data selecting unit is for selecting one of the data sampled at the first time or the second time from the sampling data in accordance to whether the sampling data is transited to output the selected one as selection data. The data recovery unit is for recovering the selection data to internal data in the same logic level as the logic level of the external data. | 10-15-2009 |
20100064163 | DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - A domain crossing circuit of a semiconductor memory apparatus, the domain crossing circuit comprising first and second count signals generated at substantially a same clock period, and representing predetermined clock differences with reference to an internal clock signal with respect to same bit combination data, and a data processing unit configured to provide output data corresponding to input data based on the second count signal in response to the input data synchronized to an external clock signal. | 03-11-2010 |
20100117702 | DUTY CYCLE CORRECTION APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT HAVING THE SAME - A duty cycle correction apparatus includes a fixed delay unit configured to set a fixed delay time to a DLL clock signal and generate a delay rising clock signal; a variable delay unit configured to delay the DLL clock signal in response to a control signal and generate a delay falling clock signal; a duty cycle correction unit configured to generate a correction rising clock signal and a correction falling clock signal that are toggled in conformity with edge timing of the delay rising clock signal and the delay falling clock signal; and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal and generate the control signal. | 05-13-2010 |
Yool-Guk Kim, Ichon-Si KR
Patent application number | Description | Published |
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20120044767 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device includes a plurality of unit cells. Each unit cell includes lower and upper electrodes over a substrate, a conductive organic material layer between the lower and the upper electrodes, and a nanocrystal layer located within the conductive organic material layer, wherein the nanocrystal layer includes a plurality of nanocrystals surrounded by an amorphous barrier. A read operation is performed when an input voltage is in a first voltage range. A first write operation is performed when the input voltage is in a second voltage range higher than the first voltage range. A second write operation is performed when the input voltage is in a third voltage range higher than the second voltage range. An erase operation is performed when the input voltage is higher than the third voltage range. | 02-23-2012 |
Youn-Cheul Kim, Ichon-Si KR
Patent application number | Description | Published |
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20110309866 | DELAY-LOCKED LOOP HAVING A LOOP BANDWIDTH DEPENDENCY ON PHASE ERROR - Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance. | 12-22-2011 |
20130329513 | DELAY-LOCKED LOOP HAVING A LOOP BANDWIDTH DEPENDENCY ON PHASE ERROR - Circuits, methods, and apparatus that vary one or more attributes or parameters of a closed-loop clock circuit as a function of a characteristic of its phase error. One example provides a delay-locked loop having a loop bandwidth that can be varied as a function of its phase error. In this specific example, current phase error is determined. This determination may be made directly, either by measuring phase error, or indirectly, by determining if phase error is within one or more ranges of values. Once the phase error is determined, the loop bandwidth can be set. In one example, the loop bandwidth is set by adjusting the depth, type, or depth and type of the delay-locked loop's loop filter. In this way, large phase errors can be reduced quickly by increasing loop bandwidth, while small phase errors can be used to decrease loop bandwidth, thereby improving jitter performance. | 12-12-2013 |
Youngjoon Kim, Ichon-Si KR
Patent application number | Description | Published |
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20090166886 | MOUNTABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH INTRA-STACK ENCAPSULATION - A mountable integrated circuit package system comprising: mounting a first integrated circuit device over a package carrier; mounting an interposer including a central aperture over the package carrier, an intra-stack interconnect connected between the interposer and the package carrier, and the first integrated circuit device within the central aperture; and forming an intra-stack encapsulation over the package carrier and surrounding the interposer. | 07-02-2009 |
20100007000 | PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION - A package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer. | 01-14-2010 |
20100140769 | INTEGRATED CIRCUIT PACKAGING SYSTEM USING BOTTOM FLIP CHIP DIE BONDING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate having a substrate cavity; mounting a bottom flip chip die below the substrate; mounting an internal integrated circuit die above the substrate; filling between the internal integrated circuit die and the substrate and between the bottom flip chip die and the substrate with a substance filling through the substrate cavity; and encapsulating the internal integrated circuit die with an encapsulation. | 06-10-2010 |
20110121465 | PACKAGE STACKING SYSTEM WITH MOLD CONTAMINATION PREVENTION AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer. | 05-26-2011 |
20120038040 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH STACKED LEAD AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit device to the substrate; forming a stud interconnect having stacked studs, the stud interconnect on the substrate and having a contact surface and a crown surface on an end of the stud interconnect opposite the substrate; applying an encapsulation over the integrated circuit die, over the stud interconnect, and over the substrate; and forming a cavity in the encapsulation over the stud interconnect, the contact surface and the crown surface exposed in the cavity. | 02-16-2012 |
20130075915 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CHIP STACKING AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first substrate; mounting a second substrate on the integrated circuit structure; coupling a vertical chip to the first substrate and to the second substrate; and forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate. | 03-28-2013 |
Youngmin Kim, Ichon-Si KR
Patent application number | Description | Published |
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20090194853 | SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a shielded stacked integrated circuit packaging system includes forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure. | 08-06-2009 |
20090243090 | MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS - A mock bump system includes providing a flip chip integrated circuit having an edge and forming a mock bump near the edge. | 10-01-2009 |
20090243091 | MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS - A mock bump system includes: providing a first structure having an edge; and forming a mock bump near the edge. | 10-01-2009 |
20110298107 | SHIELDED STACKED INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of a shielded stacked integrated circuit packaging system includes: forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure. | 12-08-2011 |
Young Park Kim, Ichon-Si KR
Patent application number | Description | Published |
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20110074369 | SEMICONDUCTOR APPARATUS AND CALIBRATION METHOD THEREOF - A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal. | 03-31-2011 |