Patent application number | Description | Published |
20080273286 | GUARD RING DEVICE RECEIVING DIFFERENT VOLTAGES FOR FORMING DECOUPLING CAPACITOR AND SEMICONDUCTOR DEVICE HAVING THE SAME - A semiconductor device in which a decoupling capacitor is formed by supplying different power levels to a guard ring device is disclosed. The semiconductor device includes a guard ring, having conductive rings, which surrounds a memory chip. The conductive rings are stacked in a multiplayer structure, and insulation layers are formed between the conductive rings. Voltages of different levels are applied to adjacent conductive rings. | 11-06-2008 |
20090067262 | VOLTAGE GENERATING UNIT OF SEMICONDUCTOR MEMORY DEVICE - A voltage generating unit of a semiconductor memory device makes it possible to reduce a peak current value when generating a high voltage. The voltage generating unit of the semiconductor memory device includes a detecting unit configured to detect a voltage level of a high voltage by comparing a reference voltage with a fed-back high voltage, an oscillating unit configured to generate a plurality of clock signals with different operation time points on the basis of an output signal of the detecting unit, and a plurality of pumping units configured to generate the high voltage according to pumping control signals based on the clock signals. | 03-12-2009 |
20090097296 | REDUCED SIZE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is described that includes memory banks having memory cells and are laid out as a matrix on a semiconductor chip body. The semiconductor memory device includes a first pad group having first pads that are arranged in a line between two adjoining memory banks and a second pad group having second pads that are also arranged in a line between the two adjoining memory banks parallel to the first pad group. At least one third pad group is also formed interposed between the first and second pad groups having at least one third pad allowing for a reduction in size of the semiconductor memory device. | 04-16-2009 |
20090122594 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal voltage terminal to a first or second power supply voltage according to an operation mode in response to the detection signal, and an enable control unit configured to control the driving unit in response to a control signal corresponding to the operation mode. | 05-14-2009 |
20090168585 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal. | 07-02-2009 |
20090185432 | SEMICONDUCTOR MEMORY DEVICE - A charge driving circuit and a discharge driving circuit occupy a relatively small area and maintain driving force in a semiconductor memory device having a plurality of banks. The semiconductor memory device includes multiple banks, a common discharge level detector configured to detect a voltage level of internal voltage terminals on the basis of a first target level in response to active signals corresponding to the respective banks, and a discharge drivers assigned to the respective banks. The discharge drivers are configured to drive the internal voltage terminals to be discharged in response to the respective active signals and respective discharge control signals outputted from the common discharge level detector. | 07-23-2009 |
20100020623 | CIRCUIT AND METHOD OF GENERATING VOLTAGE OF SEMICONDUCTOR MEMORY APPARATUS - A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and a voltage maintaining unit that maintains the first voltage in response to the driving control signal. | 01-28-2010 |
20100074043 | SEMICONDUCTOR DEVICE - A semiconductor device includes an internal circuit configured to receive a first power supply voltage applied via a first power input terminal through a first power supply path and receive an internal power supply voltage to perform a predetermined circuit operation and an internal power supply voltage generator configured to receive a second power supply voltage for a power circuit applied via a second power input terminal through a second power supply path and generate the internal power supply voltage, wherein the second power supply path is separated from the first power supply path. | 03-25-2010 |
20100118639 | SEMICONDUCTOR MEMORY APPARATUS - A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference voltage. A command buffer generates an internal command by buffering an external command in accordance with the selection reference voltage. A data buffer generates internal data by buffering an external data in accordance with the second external reference voltage. | 05-13-2010 |
20100123513 | INTERGRATED CIRCUIT FOR GENERATING INTERNAL VOLTAGE - An integrated circuit includes a driver configured to provide an internal voltage by driving an internal voltage node with an external voltage, a controller configured to output a control signal, and a discharger configured to discharge leakage current flowing into the internal voltage node through the driver in response to the control signal. | 05-20-2010 |
20100244854 | SEMICONDUCTOR DEVICE AND INTERFACE BOARD FOR TESTING THE SAME - A semiconductor device includes a common probing pad; an internal voltage generation unit having a plurality of internal voltage generation blocks configured to generate a plurality of internal voltages; and a probing voltage selection unit configured to transfer an internal voltage selected from the internal voltages to the common probing pad in response to a plurality of voltage selection signals. | 09-30-2010 |
20100315133 | POWER-UP CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICE - A power-up circuit for a semiconductor memory device includes a voltage division unit configured to divide a power supply voltage, a first power-up generation unit configured to detect a voltage level of a first divided voltage of the voltage division unit during an initial stage of applying a power supply to generate a first power-up signal and a second power-up generation unit configured to detect a voltage level of a second divided voltage of the voltage division unit, after the first power-up signal is generated from the first power-up generation unit, to generate a second power-up signal. | 12-16-2010 |
20110221411 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal. | 09-15-2011 |
20110273924 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is provided which includes a voltage detecting unit configured to compare a target voltage level with a fed-back internal voltage to output a detection signal in a normal mode, a driving unit configured to selectively drive an internal voltage terminal to a first or second power supply voltage according to an operation mode in response to the detection signal, and an enable control unit configured to control the driving unit in response to a control signal corresponding to the operation mode. | 11-10-2011 |
20120014203 | SEMICONDUCTOR MEMORY APPARATUS - A reference voltage selecting unit selectively outputs a first external reference voltage and a second external reference voltage as a selection reference voltage in accordance with whether to perform a wafer test. An address buffer generates an internal address by buffering an external address in accordance with the selection reference voltage. A command buffer generates an internal command by buffering an external command in accordance with the selection reference voltage. A data buffer generates internal data by buffering to an external data in accordance with the second external reference voltage. | 01-19-2012 |
20120105141 | INTERNAL VOLTAGE GENERATION CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - An internal voltage generation circuit includes an internal reference voltage generation unit configured to generate first and second reference voltages, a core voltage generation unit configured to receive the first reference voltage and to generate a core voltage based on the first reference voltage, and a bit line pre-charge voltage generation unit configured to receive the second reference voltage and to generate a bit-line pre-charge voltage based on the second reference voltage. | 05-03-2012 |