# Kenta Yamada, Kanagawa JP

## Kenta Yamada, Kanagawa JP

Patent application number | Description | Published |
---|---|---|

20080263495 | Software product for semiconductor device design - A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns. | 10-23-2008 |

20090024968 | Method of designing semiconductor integrated circuit and mask data generation program - A method of designing a semiconductor integrated circuit includes: generating a layout data indicating a layout; and generating a mask data based on the layout data. The generating the mask data includes: referring to the layout data to extract a parameter that specifies a layout pattern around a target transistor included in the semiconductor integrated circuit, wherein the parameter includes at least a width of a device isolation structure around the target transistor; correcting a gate length and a gate width of the target transistor to offset a variation of a characteristic of the target transistor from a design value, the variation depending on the extracted parameter; and generating the mask data from the layout data in which the gate length and the gate width are corrected. | 01-22-2009 |

20090024973 | Method and program for designing semiconductor integrated circuit - A method of designing a semiconductor integrated circuit includes: performing a circuit simulation of a cell with changing a parameter that specifies a layout pattern around the cell; and generating a delay function expressing a delay value of the cell as a function of the parameter, based on a result of the circuit simulation. The method further includes: generating a layout data indicating a layout of the semiconductor integrated circuit, based on a cell-based design technique. The method further includes: referring to the generated layout data to extract the parameter associated with a target cell included in the semiconductor integrated circuit; and calculating a delay value of the target cell by using the extracted parameter and the delay function. | 01-22-2009 |

20090024974 | Method and program for designing semiconductor integrated circuit - A design method for an LSI includes: generating a delay library for use in a statistical STA, wherein the delay library provides a delay function that expresses a cell delay value as a function of model parameters of a transistor; generating a layout data; and calculating a delay value of a target cell based on the delay library and the layout data. The calculating includes: referring to the layout data to extract a parameter specifying a layout pattern around a target transistor; modulating model parameters of the target transistor such that the characteristics corresponding to the extracted parameter is obtained in a circuit simulation; calculating, by using the delay function, a reference delay value of the target cell; and calculating, by using the delay function and the modulation amount of the model parameter, a delay variation from the reference delay value depending on the modulation amount. | 01-22-2009 |

20090070725 | Method and system for manufacturing a semiconductor device having plural wiring layers - A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns. | 03-12-2009 |

20090089037 | Method and apparatus for circuit simulation in view of stress exerted on MOS transistor - A circuit simulation method includes: generating graphical data indicating dimensions of a subject MOS transistor; calculating a parameter correction amount based on said graphical data; correcting a given transistor model parameter in response to said parameter correction amount; and performing circuit simulation of a circuit that includes said subject MOS transistor by using said corrected transistor model parameter. The parameter correction amount is calculated based on said graphical data by using arithmetic equations. The arithmetic equations include at least one stress model equation expressing a stress exerted on a channel region of a model MOS transistor. The stress model equation is suitably defined to simulate the stress exerted on the channel region. | 04-02-2009 |

20110066410 | CIRCUIT SIMULATION METHOD - A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a well resistor comprising a terminal region and a main body; and a plurality of contacts formed above the terminal region, the simulation method comprising: modeling a parasitic resistance Rt | 03-17-2011 |

20110066418 | CIRCUIT SIMULATION METHOD - A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts. | 03-17-2011 |