Patent application number | Description | Published |
20080232461 | Multi-Decoder and Method - A multi-decoder includes a plurality of decoders for different types of coding, an output buffer which stores and outputs the decoded output signal output from the decoders, an output switcher which selectively outputs the decoded output signal of the output buffer, and a controller which determines a coding scheme of the stream based on data of the header area of a stream inputted to each of the decoders, and outputs the stream to the corresponding decoder based on the determination result, and controls the output switcher to switch a decoded output signal of a sender to another decoded output signal, when inputting a stream switching signal. | 09-25-2008 |
20100325390 | IMAGE PROCESSING APPARATUS, PROCESSING UNIT, AND IP ADDRESS MANAGING METHOD - An image processing apparatus includes connectors to each of which position information is allocated, processing units configured to be connected to the connectors, each of the processing units is configured to read position information, and to output an IP address of the processing unit determined based on the position information and identification information which denotes a function of the processing unit via the connector, and a control unit configured to be connected with the connectors in compliance with a standard for a transmission line in an IP (internet protocol) network, and to manage the IP address and the identification information of the processing unit. | 12-23-2010 |
20110066883 | DATA STORAGE APPARATUS AND DATA WRITING/READING METHOD - According to one embodiment, a data storage apparatus includes a RAID controller, error detectors, and memory units. The RAID controller receives an encoded data stream, divides the encoded data stream into a predetermined number of data blocks and generates a block of parity data. The data blocks and the parity data block are distributed to the error detectors. The error detectors add an error detection code to the data blocks and the parity data block, respectively. The memory units receive the data blocks and the parity data block from the error detectors and set the data blocks and the parity data block to have the writable page units, respectively. Each of the memory units includes a plurality of memory chips and a memory controller. The memory controllers write the data blocks and the parity data block of the writable page units in the memory chips. | 03-17-2011 |
20110122320 | BROADCAST CONTENTS DATA TRANSMITTING APPARATUS AND CONTENTS DATA TRANSMITTING METHOD - According to one embodiment, a broadcast contents data transmitting apparatus includes a switcher, transmission-side processors and reception-side processors. The transmission-side processor includes a transmitter is configured to transmit the contents data stored in the recording medium to the switcher, as data units smaller than one data block that is a management unit of contents data. The switcher includes a transmission buffer configured to store the contents data transmitted from the transmission-side processor and to transmit the contents data to the reception-side processor. | 05-26-2011 |
20110231737 | DATA STORAGE APPARATUS AND DATA WRITING/READING METHOD - According to one embodiment, a data storage apparatus including memory chips includes an error correction encoder, a RAID controller, error detectors and memory units. Each of the memory chips includes a semiconductor memory. The error correction encoder adds an error correction code to an encoded data stream. The RAID controller divides the encoded data stream from the error correction encoder into data blocks. The RAID controller generates a parity data block based on the data blocks. The RAID controller outputs the data blocks and parity data block to the error detectors, respectively. The error detectors add an error detection code to the data blocks and parity data block output from the RAID controller. Each of the memory units includes the memory chips. The memory units write the data blocks and parity data block from the error detectors to the memory chips. | 09-22-2011 |
20120163779 | VIDEO SERVER AND SEAMLESS PLAYBACK METHOD - According to one embodiment, a video server includes a storage unit, an output processing unit, and a decoding processing unit. The storage unit stores first video data items and second video data items. The output processing unit generates first and second data blocks based on the first video data items and the second video data item read from the storage unit, respectively. The output processing unit outputs the first data blocks in fewer frames than usual, and outputs the second data block in vacant frame. The decoding processing unit decodes the first data blocks to generate a first playback signals, and outputs the first playback signals. The decoding processing unit stores the second data blocks. | 06-28-2012 |
20120307911 | VIDEO SERVER AND DATA RECORDING AND PLAYBACK METHOD - According to one embodiment, a video server includes an analyzer and a storage. The analyzer detects a sequence parameter set (SPS) and a picture parameter set (PPS) in a stream of a data file includes picture slices, SPSs and PPSs. The analyzer stores the detected SPS and PPS. When the analyzer detects a first picture slice in a random access unit (RAU) in the stream, the analyzer generates an additional header including all SPSs and PPSs in the stream of the data file, which are stored before detection of the first picture slice. The analyzer inserts the additional header immediately before the RAU. The storage stores the data file in which the additional header is inserted. | 12-06-2012 |
20130287372 | MULTIFORMAT VIDEO PLAYBACK DEVICE AND CONTROL METHOD THEREOF - According to one embodiment, a controller of a multiformat video playback device creates control information including a conversion instruction intended for an input processor, size specification intended for a scaler, and format specification intended for an output processor, and supplies the created control information to the input processor. A first delay section delays the control information supplied to the input processor by one frame, and supplies the delayed control information to the scaler. A second delay section delays the control information supplied to the scaler by one frame, and supplies the resultant control information to the output processor. | 10-31-2013 |