Patent application number | Description | Published |
20100237891 | Method, apparatus and system of parallel IC test - A method, apparatus and system for integrated circuit testing, wherein a plural number of devices under test (DUTs) and a plural number of comparison apparatuses are placed on a common substrate. The DUTs all operate under the same input stimulation and each produce its own operation output. The outputs are compared by the comparison apparatuses to generate comparison characteristics which are used to filter-out the failed devices. This invention lowers the testing cost, shortens time to product mass-production, and lowers the miss rate of failed devices passed as good ones. | 09-23-2010 |
20110231616 | DATA PROCESSING METHOD AND SYSTEM - A configurable multi-core structure is provided for executing a program. The configurable multi-core structure includes a plurality of processor cores and a plurality of configurable local memory respectively associated with the plurality of processor cores. The configurable multi-core structure also includes a plurality of configurable interconnect structures for serially interconnecting the plurality of processor cores. Further, each processor core is configured to execute a segment of the program in a sequential order such that the serially-interconnected processor cores execute the entire program in a pipelined way. In addition, the segment of the program for one processor core is stored in the configurable local memory associated with the one processor core along with operation data to and from the one processor core. | 09-22-2011 |
20110238917 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions, Further, the cache control unit is also configured to examine instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information, to create a plurality of tracks based on the extracted instruction information; and to fill the at least one or more instructions based on one or more tracks from the plurality of instruction tracks, | 09-29-2011 |
20110264894 | BRANCHING PROCESSING METHOD AND SYSTEM - A method is provided for controlling a pipeline operation of a processor. The processor is coupled to a memory containing executable computer instructions. The method includes determining a branch instruction to be executed by the processor, and providing both an address of a branch target instruction of the branch instruction and an address of a next instruction following the branch instruction in a program sequence. The method also includes determining a branch decision with respect to the branch instruction based on at least the address of the branch target instruction provided, and selecting at least one of the branch target instruction and the next instruction as a proper instruction to be executed by an execution unit of the processor, based on the branch decision and before the branch instruction is executed by the execution unit, such that the pipeline operation is not stalled whether or not a branch is taken with respect to the branch instruction. | 10-27-2011 |
20120191967 | CONFIGURABLE DATA PROCESSING SYSTEM AND METHOD - A reconfigurable data processing platform is disclosed. The reconfigurable data processing platform includes a reconfigurable universal data processing module, a configuration memory, and a reconfiguration control unit. The reconfigurable universal data processing module contains a plurality of basic units each capable of being configured to perform a unit of at least one of a logic operation and an arithmetic operation. The configuration memory is coupled to the reconfigurable universal data processing module to provide configuration information to be used to configure the plurality of basic units. Further, the reconfiguration control unit is coupled to the reconfigurable universal data processing module and the configuration memory to provide control signals for configuration of the plurality of basic units. | 07-26-2012 |
20120265951 | WIDE BANDWIDTH READ AND WRITE MEMORY SYSTEM AND METHOD - A memory device includes a first memory array, a first read port, a second read port, and a control input port. The first memory array contains a plurality of memory cells arranged in an array configuration. The first read port is configured to read first data from a single memory cell during a single read cycle, and the second read port is configured to read second data from a group of memory cells controlled by a common word line. Further, the control input is configured to receive a mode signal indicating a functional mode for the memory device including a first read mode and a second read mode. When the mode signal indicates the first read mode, the first read port is used to read the first data. When the mode signal indicates the second read mode, the first read port is used to read out the first data and the second read port is used to read the second data. | 10-18-2012 |
20120278590 | RECONFIGURABLE PROCESSING SYSTEM AND METHOD - A reconfigurable processor is provided. The reconfigurable processor includes a plurality of functional blocks configured to perform corresponding operations. The reconfigurable processor also includes one or more data inputs coupled to the plurality of functional blocks to provide one or more operands to the plurality of functional blocks, and one or more data outputs to provide at least one result outputted from the plurality of functional blocks. Further, the reconfigurable processor includes a plurality of devices configured to inter-connect the plurality of functional blocks such that the plurality of functional blocks are independently provided with corresponding operands from the data inputs and individual results from the plurality of functional blocks are independently feedback as operands to the plurality of functional blocks to carry out one or more operation sequences | 11-01-2012 |
20130111137 | PROCESSOR-CACHE SYSTEM AND METHOD | 05-02-2013 |
20130185545 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system includes a processor core and a cache control unit. The processor core can be coupled to a first memory containing data and a second memory with a faster speed than the first memory, and is configured to execute a segment of instructions having at least one instruction accessing the data from the second memory using a base register. The cache control unit is configured to be coupled to the first memory, the second memory, and the processor core to fill the data from the first memory to the second memory before the processor core executes the instruction accessing the data, and is further configured to examine the segment of instructions to extract instruction information containing at least data access instruction information and last register updating instruction information and to create a track corresponding to the segment of instructions based on the extracted instruction information. | 07-18-2013 |
20130339611 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions. Further, the cache control unit is also configured to examine instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information, to create a plurality of tracks based on the extracted instruction information; and to fill the at least one or more instructions based on one or more tracks from the plurality of instruction tracks. | 12-19-2013 |
20140337582 | HIGH-PERFORMANCE CACHE SYSTEM AND METHOD - A digital system is provided for high-performance cache systems. The digital system includes a processor core and a cache control unit. The processor core is capable of being coupled to a first memory containing executable instructions and a second memory with a faster speed than the first memory. Further, the processor core is configured to execute one or more instructions of the executable instructions from the second memory. The cache control unit is configured to be couple to the first memory, the second memory, and the processor core to fill at least the one or more instructions from the first memory to the second memory before the processor core executes the one or more instructions. Further, the cache control unit is also configured to examine instructions being filled from the first memory to the second memory to extract instruction information containing at least branch information, to create a plurality of tracks based on the extracted instruction information; and to fill the at least one or more instructions based on one or more tracks from the plurality of instruction tracks. | 11-13-2014 |