Patent application number | Description | Published |
20080298153 | Semiconductor memory device - The present invention provides a semiconductor memory device with an open bit line structure in which sense amplifiers are arranged in a zigzag pattern and a plurality of banks, each having a plurality of mats, are provided. The semiconductor memory device includes: a refresh counter that counts the number of refresh commands and generates word line addresses; pre-decoders, each of which is provided for a corresponding bank, and which pre-decodes the word line address and outputs a pre-decode signal for selecting a mat row; bit arrangement changing circuits each of which changes the arrangement of bits of the pre-decode signal when a refresh signal indicating a refresh operation is input; and X decoders each of which outputs signals for driving a mat row and a word line according to the pre-decode signal and the word line address. | 12-04-2008 |
20080298154 | Semiconductor memory device - A semiconductor memory device includes: a plurality of banks each of which includes a plurality of mats each having normal word lines and redundant word lines; a first refresh generating circuit that generates a first refresh start signal for performing a first refresh operation in response to input of a refresh command; and a second refresh generating circuit that generates a second refresh start signal for performing a second refresh operation in response to a refresh operation end signal indicating that the first refresh operation ends. | 12-04-2008 |
20090268514 | Semiconductor memory device and control method thereof - A semiconductor memory device includes: a plurality of word lines; a plurality of bit lines; plurality of memory cells arranged at intersections of the word lines and the bit lines; a word driver that selects any one of the word lines; a plurality of sense amplifiers connectable to any of the bit lines; a sense-amplifier starting circuit that sequentially starts the sense amplifiers in response to a request of consecutive read operations to the memory cells connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver; and an address determining circuit that temporarily stops an operation of the sense-amplifier starting circuit in response to a request of consecutive read operations to a same memory cell connected to a predetermined word line, in a state that the predetermined word line is selected by the word driver. | 10-29-2009 |
20100085804 | SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM INCLUDING THE SAME - In synchronism with an active command, a row address and a column address are simultaneously received, and a page address is received in synchronism with a read command or a write command. Word drivers select a word line based on the row address, and column switches select a bit line based on the column address. A page address decoder selects any one of read/write amplifiers corresponding to each page based on the page address. With this configuration, a specification for a DRAM such as an access cycle can be satisfied without arranging an amplifier for each bit line, and thus it becomes possible to secure a compatibility with a DRAM while reducing a chip area. | 04-08-2010 |
20100124104 | Memory device and writing method thereof - A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability. | 05-20-2010 |
20130058154 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a plurality of first memory cells, at least one of second memory cells, and a control circuit. The plurality of first memory cells are accessed during normal operation, wherein the first memory cell includes a first variable resistance element. The second memory cell is not accessed during the normal operation but accessed at a time of test operation. The second memory cell includes a second variable resistance element practically identical to the first variable resistance element. The control circuit performs forming on the second memory cell at the time of the test operation. | 03-07-2013 |
20140085964 | SEMICONDUCTOR STORAGE DEVICE - A control circuit controls memory operations such that, in a first rewriting operation in which a resistance state of a variable resistance element is changed from a first state to a second state, a first voltage pulse is applied to both terminals of a memory cell while limiting the amount of current flowing through the variable resistance element to a value smaller than or equal to a certain small amount of current, in a second rewriting operation in which the resistance state of the variable resistance element is changed from the second state to the first state, a second voltage pulse is applied to both terminals of the memory cell, and, in a reading operation in which the resistance state stored in the variable resistance element is read, a third voltage pulse is applied to both terminals of the memory cell. | 03-27-2014 |
20140092679 | MEMORY DEVICE AND WRITING METHOD THEREOF - A write amplifier for driving a bit line connected to a selected phase change memory cell drives the bit line with a first current driving capability and then drives the bit line with a second current driving capability lower than the first current driving capability. | 04-03-2014 |
20140140125 | SEMICONDUCTOR DEVICE AND CONTROL METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device is provided with the variable resistance element, and a control circuit that controls a resistance state of the variable resistance element by controlling current between a first end and a second end of the variable resistance element. The control circuit causes the variable resistance element to change from a first resistance state to a second resistance state by having a first current flow from the first end to the second end of the variable resistance element. In addition, after a second current smaller than the first current is made to flow from the first end to the second end of the variable resistance element, the control circuit causes the variable resistance element to change from the second resistance state to the first resistance state by having a third current flow from the second end to the first end thereof. | 05-22-2014 |