Patent application number | Description | Published |
20090083478 | INTEGRATED MEMORY MANAGEMENT AND MEMORY MANAGEMENT METHOD - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory. | 03-26-2009 |
20100064111 | INFORMATION PROCESSING DEVICE INCLUDING MEMORY MANAGEMENT DEVICE MANAGING ACCESS FROM PROCESSOR TO MEMORY AND MEMORY MANAGEMENT METHOD - A device according to an example of the invention comprises a section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory, a section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory, a section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address, and a section which writes the write target data into a position in the composite memory indicated by the write destination physical address. | 03-11-2010 |
20120124290 | Integrated Memory Management and Memory Management Method - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory. | 05-17-2012 |
20120191900 | MEMORY MANAGEMENT DEVICE - A memory management device of an example of the invention controls writing into and reading from a main memory including a nonvolatile semiconductor memory and a volatile semiconductor memory in response to a writing request and a reading request from a processor. The memory management device includes a coloring information storage unit that stores coloring information generated based on a data characteristic of write target data to be written into at least one of the nonvolatile semiconductor memory and the volatile semiconductor memory, and a writing management unit that references the coloring information to determines a region into which the write target data is written from the nonvolatile semiconductor memory and the volatile semiconductor memory. | 07-26-2012 |
20120216003 | SEMICONDUCTOR DEVICE AND MEMORY PROTECTION METHOD - According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets. | 08-23-2012 |
20130191609 | INFORMATION PROCESSING DEVICE INCLUDING HOST DEVICE AND SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY DEVICE - A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information. | 07-25-2013 |
20130254471 | DEVICE AND MEMORY SYSTEM FOR MEMORY MANAGEMENT USING ACCESS FREQUENCY INFORMATION - An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory. | 09-26-2013 |
20150046634 | MEMORY SYSTEM AND INFORMATION PROCESSING DEVICE - According to embodiments a memory system is connectable to a host which includes a host controller and a host memory including a first memory area and a second memory area. The memory system includes an interface unit, a non-volatile memory, and a controller unit. The interface unit receives a read command and a write command. The controller unit writes write-data to the non-volatile memory according to the write command. The controller unit determines whether read-data requested by the read command is in the first memory area. If the read-data is in the first memory area, the controller unit causes the host controller to copy the read-data from the first memory area to the second memory area. If the read-data is not in the first memory area, the controller unit reads the read-data from the non-volatile memory and causes the host controller to store the read-data in the second memory area. | 02-12-2015 |
20150058588 | SEMICONDUCTOR DEVICE AND MEMORY PROTECTION METHOD - According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets. | 02-26-2015 |
20150071155 | COMMUNICATION APPARATUS AND COMMUNICATION METHOD - According to the embodiments, a communication apparatus stores therein an operation mode indicating whether the communication apparatus is a publisher or a subscriber, and includes a message processing unit that generates a transmission message and analyzes a reception message and a nonvolatile memory. When the communication apparatus is subscriber, the communication apparatus sends a repair message to request a retransmission of a data chunk not successively received. When the communication apparatus is publisher, the communication apparatus selectively retransmits the data chunk based on the repair message. | 03-12-2015 |
20150071156 | COMMUNICATION APPARATUS AND COMMUNICATION METHOD - According to the embodiments, when a communication apparatus is a publisher, a transmission message including a first identifier is transmitted using first transmission power, when the communication apparatus is a subscriber, data of a reception message including the first identifier is stored in a nonvolatile memory, when at least a part of the reception message cannot be received, a repair message for requesting retransmission of the reception message is transmitted from a wireless interface unit using second transmission power, and when there is no response, a repair message is transmitted using third transmission power that is larger than the second transmission power. | 03-12-2015 |
20150074329 | INFORMATION PROCESSING DEVICE - A device of one embodiment includes a host device including a first memory unit and host controller, and memory device. The host controller controls input/output accesses to the first memory unit. The memory device includes a nonvolatile semiconductor memory, second memory unit, protection circuit, and device controller. The second memory unit temporarily stores data to be transferred between the first memory unit and the nonvolatile semiconductor memory. The protection circuit protects data to be transferred from the second memory unit to the first memory unit by converting the data into an incomprehensible format. The device controller switches according to a control program whether or not to protect the data by the protection circuit. | 03-12-2015 |
Patent application number | Description | Published |
20120064402 | LEAD-ACID BATTERY AND METHOD FOR MANUFACTURING CURRENT COLLECTOR FOR LEAD-ACID BATTERY - Provided herein is a lead-acid battery for which the risk of breakage of a current collecting lug part of a plate while in use is eliminated by simple means. At least a positive plate group of the lead-acid battery includes: one or more plates each including a current collector having a current collecting portion formed by expanding or punching a lead alloy sheet manufactured by cold rolling, and one or more current collecting lug parts unitarily formed with the current collecting portion; and a strap formed by a cast-on strap casting method and coupled to the one or more current collecting lug parts. The current collecting lug part is formed with an elongated protrusion extending in a direction away from the current collecting portion. The elongated protrusion continuously extends in a direction toward the current collecting portion of the plate from inside the strap. | 03-15-2012 |
20130026784 | SADDLE-RIDING TYPE VEHICLE INCLUDING MULTI-PART SHROUD - In a saddle-riding type vehicle including a shroud, efficiency is achieved by disposing a vehicle component in a space shielded by the shroud, and the vehicle component is suitably protected from, for example, rainwater, while ventilation for the vehicle component is ensured. A regulator is disposed on a first side of the vehicle, at a position at which the regulator does not overlap a fuel tank as seen in a top plan view. The regulator is covered by a right shroud from above and from outside in the vehicle width direction. The right shroud has an opening formed therein at a portion where the regulator faces upwardly. The opening overlaps with, and is covered by from above by part of the right shroud that is different from the portion of the right shroud at which the opening is formed in a top plan view. | 01-31-2013 |
20150180048 | LEAD-ACID BATTERY AND METHOD FOR MANUFACTURING CURRENT COLLECTOR FOR LEAD-ACID BATTERY - Provided herein is a lead-acid battery for which the risk of breakage of a current collecting lug part of a plate while in use is eliminated by simple means. At least a positive plate group of the lead-acid battery includes: one or more plates each including a current collector having a current collecting portion formed by expanding or punching a lead alloy sheet manufactured by cold rolling, and one or more current collecting lug parts unitarily formed with the current collecting portion; and a strap formed by a cast-on strap casting method and coupled to the one or more current collecting lug parts. The current collecting lug part is formed with an elongated protrusion extending in a direction away from the current collecting portion. The elongated protrusion continuously extends in a direction toward the current collecting portion of the plate from inside the strap. | 06-25-2015 |