Patent application number | Description | Published |
20080283870 | FIELD-EFFECT SEMICONDUCTOR DEVICE - A HEMT-type field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on the main semiconductor region. Between these electrodes, with spacings therefrom, an insulator is provided with is made from a material capable of developing a stress to reduce carrier concentration in neighboring part of the two-dimensional electron gas layer, creating a discontinuity in this layer. A gate electrode overlies the insulator via a piezoelectric layer which is made from a material capable of developing, in response to a voltage applied to the gate electrode, a stress for canceling out the stress developed by the insulator. Thus the device is physically held off by the action of the insulator while no voltage is being impressed to the gate electrode and, upon voltage application thereto, piezoelectrically turns on by the action of the piezoelectric layer. The turn-on resistance of the device is relatively low as the insulator occupies only part of the source-drain spacing. | 11-20-2008 |
20080303064 | FIELD-EFFECT SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION - After creating an electron transit layer on a substrate, a baffle is formed on midpart of the surface of the electron transit layer, the surface having a pair of spaced-apart parts left on both sides of the baffle. A semiconducting material different from that of the electron transit layer is deposited on its surface thereby conjointly fabricating an electron supply layer grown continuously on the pair of spaced-apart parts of the electron transit layer surface, and a discontinuous growth layer on the baffle in the midpart of the electron transit layer surface. When no voltage is being impressed to the gate electrode on the discontinuous growth layer, this layer creates a hiatus in the two-dimensional electron gas layer generated along the heterojunction between the electron supply layer and electron transit layer. The hiatus is closed upon voltage application to the gate electrode. | 12-11-2008 |
20090008676 | NORMALLY-OFF FIELD-EFFECT SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATION - A normally-off HEMT is made by first providing a substrate having its surface partly covered with an antigrowth mask. Gallium nitride is grown by epitaxy on the masked surface of the substrate to provide an electron transit layer comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections are formed on unmasked parts of the substrate surface whereas the V-notch-surfaced section, defining a V-sectioned notch, is created by lateral overgrowth onto the antigrowth mask. Aluminum gallium nitride is then deposited on the electron transit layer to provide an electron supply layer which is likewise comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections of the electron supply layer are sufficiently thick to normally generate two-dimensional electron gas layers due to heterojunctions thereof with the first and the second flat-surfaced section of the electron transit layer. The V-notch-surfaced section of the electron supply layer is not so thick, normally creating an interruption in the two-dimensional electron gas layer. | 01-08-2009 |
20090212325 | Hetero Field Effect Transistor and Manufacturing Method Thereof - A hetero field effect transistor includes: a main semiconductor region including a first semiconductor layer and a second semiconductor layer formed thereon to allow a generation of a two-dimensional carrier gas layer of a first conductive type on a heterojunction interface therebetween; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third semiconductor layer of a second conductive type different from the first conductive type, the third semiconductor layer being formed on the second semiconductor layer and located between the source electrode and the drain electrode; and a gate electrode formed on the third semiconductor layer. A concave portion is formed in an upper surface of the second semiconductor layer at a region immediately below the gate electrode. | 08-27-2009 |
20090212326 | Hetero Field Effect Transistor and Manufacturing Method Thereof - A hetero field effect transistor includes: a first semiconductor layer; a second semiconductor layer formed on the first semiconductor layer to allow a generation of a two dimensional carrier gas layer of a first conductive type on a heterojunction interface between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the second semiconductor layer and having an impurity introduced therein; a source electrode formed on the third semiconductor layer; a drain electrode formed on the third semiconductor layer and separated from the source electrode; a fourth semiconductor layer formed on or above the second semiconductor layer and has a second conductive type which is different from the first conductive type; and a gate electrode electrically connected on the fourth semiconductor layer. The fourth semiconductor layer is located adjacent to and surrounded by the third semiconductor layer. | 08-27-2009 |
20100012978 | NORMALLY-OFF FIELD-EFFECT SEMICONDUCTOR DEVICE - A normally-off HEMT is made by first providing a substrate having its surface partly covered with an antigrowth mask. Gallium nitride is grown by epitaxy on the masked surface of the substrate to provide an electron transit layer comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections are formed on unmasked parts of the substrate surface whereas the V-notch-surfaced section, defining a V-sectioned notch, is created by lateral overgrowth onto the antigrowth mask. Aluminum gallium nitride is then deposited on the electron transit layer to provide an electron supply layer which is likewise comprised of two flat-surfaced sections and a V-notch-surfaced section therebetween. The flat-surfaced sections of the electron supply layer are sufficiently thick to normally generate two-dimensional electron gas layers due to heterojunctions thereof with the first and the second flat-surfaced section of the electron transit layer. The V-notch-surfaced section of the electron supply layer is not so thick, normally creating an interruption in the two-dimensional electron gas layer. | 01-21-2010 |
20100090225 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a main semiconductor region comprising a first nitride semiconductor layer having a first band gap, and a second nitride semiconductor layer having a second band gap larger than the first band gap, a heterojunction being formed between the first nitride semiconductor layer and a the second nitride semiconductor layer such that two-dimensional electron gas layer can be caused inside the first nitride semiconductor layer based on the heterojunction; a source electrode formed on the main semiconductor region; a drain electrode formed on the main semiconductor region and separated from the source electrode; a third nitride semiconductor layer formed on the first nitride semiconductor layer and between the source electrode and the drain electrode; and a gate electrode formed on the third nitride semiconductor layer. The third nitride semiconductor layer has a third band gap smaller than the first band gap. | 04-15-2010 |
20100102357 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes: a main semiconductor region comprising a first nitride semiconductor layer having a first band gap, and a second nitride semiconductor layer having a second band gap larger than the first band gap, a heterojunction being formed between the first nitride semiconductor layer and the second nitride semiconductor layer such that a two-dimensional electron gas layer can be caused inside the first nitride semiconductor layer based on the heterojunction; a source electrode; a drain electrode; a third nitride semiconductor layer formed on the first nitride semiconductor layer and between the source electrode and the drain electrode; a fourth nitride semiconductor layer formed on the third nitride semiconductor layer and having p-type conductivity; and a gate electrode formed on the fourth nitride semiconductor layer. The third nitride semiconductor layer has a third band gap smaller than the first band gap. | 04-29-2010 |
20110049527 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: an active layer, which has a composition represented by the formula: Al | 03-03-2011 |
20110073911 | SEMICONDUCTOR DEVICE - A semiconductor device including: a substrate, which has a composition represented by the formula: Al | 03-31-2011 |
20110204379 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor device including: a substrate; a nitride semiconductor layer formed on the substrate and having a heterojunction interface; and a recess portion formed on the nitride semiconductor layer, wherein the nitride semiconductor layer includes: a carrier transit layer, which has a composition represented by the formula: Al | 08-25-2011 |
20110204417 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A semiconductor device according to the present invention including: a substrate; a compound semiconductor layer formed on the substrate; an element forming area provided in the compound semiconductor layer; and at least one semiconductor element, which includes a first main electrode and a main second electrode, wherein the at least one semiconductor element is formed in the element forming area, wherein the compound semiconductor layer includes: a first compound growth layer, which is formed on the substrate and includes the element forming area; and a second compound growth layer formed on the substrate to surround the element forming area when viewed from a plane, wherein the second compound growth layer has a crystallinity lower than a crystallinity of the first compound growth layer | 08-25-2011 |
20120034768 | METHOD OF MANUFACTURING SEMICONDUCTOR WAFER - A method of manufacturing a semiconductor wafer, which includes: a semiconductor substrate made of silicon and having both a central area and an outer periphery area; and a compound semiconductor layer made of a nitride-based semiconductor and formed on the semiconductor substrate, the method comprising: forming a growth inhibition layer to inhibit the compound semiconductor layer from growing on a tapered part provided in the outer periphery area of the semiconductor substrate; and growing the compound semiconductor layer on at least the central area of the semiconductor substrate, after the growth inhibition layer has been formed. | 02-09-2012 |
20120132962 | Method of Manufacturing Semiconductor Device and Semiconductor Device - A method of manufacturing a semiconductor device, in which a second semiconductor layer of Al | 05-31-2012 |