Patent application number | Description | Published |
20080203998 | ON-CHIP POWER SUPPLY MONITOR USING LATCH DELAY SENSOR - A system for on-chip power supply monitoring by using a single latch delay sensor, including a first delay chain; a second delay chain; a latch circuit; a latch counter; and a slate machine for controlling a voltage; wherein the one or more outputs of the first and second delay chains are compared via a digital logic circuit to detect transients above or below predetermined limits in a single clock cycle; and wherein the one or more outputs of the first and second delay chains are compared via a digital logic circuit to detect transients above or below predetermined limits in a single clock cycle; and wherein a ratio of (i) a number of signals counted by the latch counter and (ii) a number of signals counted by the clock counter yields a statistical measurement of the power supply or ground transients. | 08-28-2008 |
20080258751 | On-Chip Power Supply Noise Detector - Techniques for on-chip detection of integrated circuit power supply noise are disclosed. By way of example, a technique for monitoring a power supply line in an integrated circuit includes the following steps/operations. A first signal and a second signal are preconditioned. The first signal is representative of a voltage of the power supply line being monitored. The second signal is representative of a voltage of a reference power supply line. Preconditioning includes shifting respective levels of the voltages such that the voltages are within an input voltage range of comparator circuitry. Then, the preconditioned first signal and the preconditioned second signal are compared in accordance with the comparator circuitry. Comparison includes detecting when a difference exists between the voltage level of the preconditioned first signal and the voltage level of the preconditioned second signal. | 10-23-2008 |
20080284477 | ON-CHIP JITTER MEASUREMENT CIRCUIT - An on-chip jitter measurement circuit and corresponding method are provided for receiving a reference clock and a signal of interest, including a latch for comparing the arrival time of the signal of interest to the reference clock, a delay chain in signal communication with the reference clock for varying the arrival time of the reference clock, the delay chain having a first stage, a middle stage, and a last stage, a voltage controller in signal communication with the middle stage of the delay chain for controlling the delay of the arrival time of the reference clock while permitting the first and last stages of the delay chain to retain a full voltage swing independent of the delay. | 11-20-2008 |
20080291970 | ON CHIP TEMPERATURE MEASURING AND MONITORING CIRCUIT AND METHOD - A device temperature measurement circuit, an integrated circuit (IC) including a device temperature measurement circuit, a method of characterizing device temperature and a method of monitoring temperature. The circuit includes a constant current source and a clamping device. The clamping device selectively shunts current from the constant current source or allows the current to flow through a PN junction, which may be the body to source/drain junction of a field effect transistor (FET). Voltage measurements are taken directly from the PN junction. Junction temperature is determined from measured junction voltage. | 11-27-2008 |
20080315907 | Methods of Operating an Electronic Circuit for Measurement of Transistor Variability and the Like - An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value. | 12-25-2008 |
20090063061 | MONITORING DEGRADATION OF CIRCIUT SPEED - A circuit, method, and computer readable medium that enables on-chip monitoring of transistor degradation. The circuit includes an on-chip reference ring oscillator electrically coupled to an on-chip reference counter. An on-chip stressed ring oscillator is electrically coupled to an on-chip test counter. A test enable input is electrically coupled with the reference counter, the test counter, and the reference ring oscillator. When the test enable input is asserted the reference ring oscillator places a bit sequence proportional to the reference ring oscillator frequency on the reference counter simultaneously while the stressed ring oscillator places bit sequence proportional to the stressed ring oscillator frequency on the test counter. A difference in bit sequence between the reference counter and the test counter is compared to determine a relative difference there between. | 03-05-2009 |
20090116325 | ON-CHIP CHARACTERIZATION OF NOISE-MARGINS FOR MEMORY ARRAYS - A circuit, method, and computer readable medium for on-chip measuring of noise margins in a memory device memory device are disclosed. The on-chip method includes electrically coupling at least a first circuit to a memory cell. A voltage divider is electrically coupled to at least a first voltage and a second voltage. A multiplexer circuit is electrically coupled to the voltage divider. The multiplexer selects one of the first voltage and second voltage for producing a test voltage. A selecting line is electrically coupled to a force\measure network. A comparator is coupled to the force\measure network. The force-measure network supplies the test voltage to the comparator and a measured voltage to the comparator for determining when the measured voltage exceeds the test voltage. | 05-07-2009 |
20090121736 | DISPOSABLE BUILT-IN SELF-TEST DEVICES, SYSTEMS AND METHODS FOR TESTING THREE DIMENSIONAL INTEGRATED CIRCUITS - A device and method for self-testing an integrated circuit layer for a three-dimensional integrated circuit includes integrally forming a disposable self-test circuit on a common substrate with a first circuit to be tested. The first circuit forms a layer in a three-dimensional integrated circuit structure. The first circuit is tested using circuitry of the self-test circuit. The self-test circuit is removed by detaching the self-test circuit from the first circuit. | 05-14-2009 |
20090309625 | ELECTRONIC CIRCUIT FOR MEASUREMENT OF TRANSISTOR VARIABILITY AND THE LIKE - An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value. | 12-17-2009 |
20110235390 | HIGH DENSITY MEMORY DEVICE - A memory device and a method of forming the same are provided. The memory device includes a substrate; a set of electrodes disposed on the substrate; a dielectric layer formed between the set of electrodes; and a transition metal oxide layer formed between the set of electrodes, the transition metal oxide layer configured to undergo a metal-insulator transition (MIT) to perform a read or write operation. | 09-29-2011 |
20120081141 | On-Chip Delay Measurement Through a Transistor Array - Methods and apparatus are provided for measuring a delay through one or more transistors in an array of transistors. The delay through one or more transistors in an array of transistors is measured by selecting one of the transistors in the array; and applying a clock signal to the selected transistor, wherein an output of the selected transistor is applied to a first input of a logic gate having at least two inputs and wherein a second clock signal based on the clock signal is applied to a second input of the logic gate, and wherein an output of the logic gate indicates a difference in arrival times of the signals at the two inputs. In one variation, a clock signal is applied to the selected transistor and a variable delay circuit; and an output of the selected transistor is applied to a data input of a latch having a clock input and a data input while an output of the variable delay circuit is applied to a clock input of the latch. The delay applied by the variable delay circuit to the clock signal is adjusted until a predefined transition is detected in an output of the latch. If the delay is measured through a plurality of transistors in the array, the delay variation among the plurality of transistors can be obtained. | 04-05-2012 |
20120126870 | CIRCUIT AND METHOD FOR RAS-ENABLED AND SELF-REGULATED FREQUENCY AND DELAY SENSOR - Circuits and methods are provided for a reliability, availability and serviceability (RAS) enabled and self-regulated frequency and delay sensor of a semiconductor. A circuit for measuring and compensating for time-dependent performance degradation of an integrated circuit, includes at least one critical functional path of the integrated circuit, and Wearout Isolation Registers (WIR's) connected to boundaries of the critical functional path. The circuit also includes a feedback path connected to the WIR's, and a sensor control module operable to disconnect the critical functional path from preceding and succeeding functional paths of the integrated circuit, connect the critical functional path to the feedback path to form a critical path ring oscillator (CPRO), and enable the CPRO to generate an operating signal. A delay sensor module is operable to measure a frequency of the operating signal to determine and compensate for a degradation of application performance over a lifetime of a semiconductor product. | 05-24-2012 |
20120212238 | ON-CHIP MEASUREMENT OF AC VARIABILITY IN INDIVIDUAL TRANSISTOR DEVICES - An apparatus for determining alternating current (AC) delay variation of a transistor device under test includes a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test. | 08-23-2012 |
20120300534 | HIGH DENSITY MEMORY DEVICE - A method of operating a memory device having a dielectric material layer, a transition metal oxide layer and a set of electrodes each formed over a substrate, includes applying a voltage across the set of electrodes producing an electric field across the transition metal oxide layer enabling the transition metal oxide layer to undergo a metal-insulation transition (MIT) to perform a read or write operation on memory device. | 11-29-2012 |
20120326728 | ON-CHIP MEASUREMENT OF AC VARIABILITY IN INDIVIDUAL TRANSISTOR DEVICES - An apparatus for determining alternating current (AC) delay variation of a transistor device under test includes a ring oscillator, the ring oscillator having the transistor device under test configured within a feedback path of the ring oscillator; and circuitry configured to measure a difference between a first signal delay path and a second signal delay path, the first signal delay path being between a gate terminal and a drain terminal of the transistor device under test, and the second signal delay path being between a source terminal and the drain terminal of the transistor device under test. | 12-27-2012 |
20130015837 | ON-CHIP SIGNAL WAVEFORM MEASUREMENT CIRCUITAANM Jenkins; Keith A.AACI Sleepy HollowAAST NYAACO USAAGP Jenkins; Keith A. Sleepy Hollow NY USAANM Wang; Peter Z.AACI Yorktown HeightsAAST NYAACO USAAGP Wang; Peter Z. Yorktown Heights NY US - Methods and apparatus are provided for on-chip signal waveform measurement. An integrated circuit is provided that comprises an on-chip comparator for comparing a voltage level of a signal to be measured to a voltage level of a reference voltage, at a time determined by at least one edge of an evaluation clock. The reference voltage can be varied to obtain a plurality of voltage points. The evaluation clock can be varied to obtain a plurality of time sampling points. In addition, the reference voltage and the evaluation clock can both be varied to obtain a plurality of voltage-time sampling points constituting a waveform corresponding to the signal to be measured. | 01-17-2013 |
20130212414 | REDUCING PERFORMANCE DEGRADATION IN BACKUP SEMICONDUCTOR CHIPS - A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided. | 08-15-2013 |
20140022025 | HIGH FREQUENCY OSCILLATOR CIRCUIT AND METHOD TO OPERATE SAME - A method includes providing an oscillator having a field effect transistor connected with a resonant circuit. The field effect transistor has a gate electrode coupled to a source of gate voltage, a source electrode, a drain electrode and a graphene channel disposed between the source electrode and the drain electrode and electrically connected thereto. The method further includes biasing the graphene channel via the gate electrode into a negative differential resistance region of operation to cause the oscillator to generate a frequency signal having a resonant frequency f0. There can be an additional step of varying the gate voltage so as to bias the graphene channel into the negative differential resistance region of operation and out of the negative differential resistance region of operation so as to turn on the frequency signal and to turn off the frequency signal, respectively. | 01-23-2014 |