Kee-Hoon
Kee-Hoon Hong, Seoul KR
Patent application number | Description | Published |
---|---|---|
20140285863 | METHOD AND APPARATUS FOR HOLOGRAPHIC RECORDING - Provided is a holographic recording method in which an interference fringe between a reference beam and a signal beam, modulated according to information regarding a plurality of hologram pixels, is recorded on a holographic recording medium, the holographic recording method including multiplexing-recording the interference fringe of the plurality of hologram pixels such that at least a part of the interference fringe recorded of neighboring hologram pixels of the plurality of hologram pixels is overlapped. | 09-25-2014 |
Kee-Hoon Kim, Seoul KR
Patent application number | Description | Published |
---|---|---|
20090270262 | MAGNETOELECTRIC SUSCEPTIBILITY MEASUREMENT METHOD AND THE SYSTEM THEREOF - Disclosed herein is a method and system for measuring magnetoelectric susceptibility. The system includes a magnet supplying a DC magnetic bias to a magnetoelectric sample, an AC drive coil applying an AC magnetic field to the magnetoelectric sample, a charge amplifier amplifying an electric charge signal of the magnetoelectric sample oscillating by the AC magnetic field, and a phase sensitive detector detecting the voltage signal produced by the charge amplifier while supplying induction current to the AC drive coil. Accordingly, it is possible to provide a highly sensitive system for measuring magnetoelectric susceptibility, which is essential for research on multiferroic and magnetoelectric bulk and thin film materials at room temperature, and can also operate in the physical property measurement system (PPMS, manufactured by Quantum Design Co., Ltd.) for measurements under low temperature and high magnetic field environments. | 10-29-2009 |
20110031434 | MULTIFERROIC MATERIAL AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a multiferroic material capable of freely controlling magnetic field size at room temperature, and to a method of manufacturing the same. Said multiferroic material includes hexaferrites containing magnetic iron ions partially substituted by non-magnetic ions. Said non-magnetic ions act to change the magnetic anisotropy of said hexaferrites. | 02-10-2011 |
20140138571 | MAGNETOELECTRIC MATERIAL AND METHOD OF MANUFACTURING THE SAME - The present invention provides a magnetoelectric material in which an electric property is capable of being controlled by a magnetic field or a magnetic property is capable of being controlled by an electric field, and a method of manufacturing the same. Particularly, the present invention provides a magnetoelectric material in which a distance between magnetic ions interacting with each other is controlled by using non-magnetic ions or alkaline earth metal ions, and a method of manufacturing the same. | 05-22-2014 |
Kee-Hoon Kim, Daejeon KR
Patent application number | Description | Published |
---|---|---|
20130077467 | RECEIVER IN ORTHOGONAL FREQUENCY DIVISION MULTIPLE ACCESS SYSTEM AND SIGNAL PROCESSING METHOD THEREOF - According to an exemplary embodiment of the present invention, a receiver in an orthogonal frequency division multiple access (OFDMA) system includes: an extraction unit that extracts received user signal subvectors for subcarriers assigned to the receiver from received signal vectors received from a transmitter; and a fast Fourier transform (FFT) unit that performs a fast Fourier transform on the received user signal subvectors. | 03-28-2013 |
Kee-Hoon Lee, Gyeonggi-Do KR
Patent application number | Description | Published |
---|---|---|
20090059680 | Integrated Circuit Memory Devices That Support Selective Mode Register Set Commands - A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrated circuit memory devices over the command/address bus during a mode register set operation. A disable signal may be provided from the memory controller to a first one of the integrated circuit memory devices over a signal line between the memory controller and the first integrated circuit memory device to thereby disable implementation of the mode register set command for the first integrated circuit memory device during the mode register set operation. An enable signal may be provided from the memory controller to a second one of the integrated circuit memory devices over a signal line between the memory controller and the second integrated circuit memory device to thereby enable implementation of the mode register set command for the second integrated circuit memory device during the mode register set operation. Moreover, the disable signal may not be provided to the second integrated circuit memory device during the mode register set operation, and the enable signal may not be provided to the first integrated circuit memory device during the mode register set operation. Related systems, devices and additional methods are also discussed. | 03-05-2009 |
20100054053 | Integrated Circuit Memory Devices Including Mode Registers Set Using A Data Input/Output Bus - An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed. | 03-04-2010 |
Kee-Hoon Lee, Seoul KR
Patent application number | Description | Published |
---|---|---|
20080320186 | MEMORY DEVICE CAPABLE OF COMMUNICATING WITH HOST AT DIFFERENT SPEEDS, AND DATA COMMUNICATION SYSTEM USING THE MEMORY DEVICE - Provided is a memory device for high speed communication including a low speed data communication port and a low speed data input/output circuit, and a data communication system using the memory device. The memory device includes a high speed port interface for transmitting or receiving data to or from a host at a high speed, and a low speed port interface for transmitting or receiving data to or from the host at a low speed. | 12-25-2008 |
20090300236 | MEMORY DEVICE COMMUNICATING WITH A HOST AT DIFFERENT SPEEDS AND MANAGING ACCESS TO SHARED MEMORY - A memory device includes a high speed port, a low speed port, at least a first memory bank, a first register, and a multiplexer. The at least first memory bank is shared by the high speed port and the low speed port. The first register store information that indicates which one of the ports has permission to access the first memory bank. The multiplexer connects one of the high speed port or the low speed port to the first memory bank, in response to the information stored in the first register. | 12-03-2009 |
Kee-Hoon Lee, Seocho-Gu KR
Patent application number | Description | Published |
---|---|---|
20080228973 | MEMORY CARD HAVING PLURALITY OF INTERFACE PORTS, MEMORY CARD SYSTEM, AND DATA COMMUNICATION METHOD FOR THE MEMORY CARD - A memory card is disclosed including first and second host interfaces facilitating the communication of data between the memory card and a host using, respectively, first and second protocols, wherein the first protocol defines low-speed operations and the second protocol defines high-speed operations for the memory card. The second host interface is only enabled in response to an indication by the host device of a high-speed memory card operation. | 09-18-2008 |