Ke-Chih
Ke-Chih Chang, Taipei City TW
Patent application number | Description | Published |
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20110156038 | ACTIVE DEVICE ARRAY SUBSTRATE - An active device array substrate including a substrate, scan lines, data lines, active devices, a first dielectric layer, a common line, a second dielectric layer, a patterned conductive layer, a third dielectric layer, and pixel electrodes is provided. At least a part of the active devices are electrically connected to the scan lines and the data lines. The first dielectric layer covers the scan lines, the data lines and the active devices. The common line is disposed on the first dielectric layer. The second dielectric layer covers the common line and the first dielectric layer. The patterned conductive layer is disposed on the second dielectric layer. The third dielectric layer covers the patterned conductive layer and the second dielectric layer. The pixel electrodes are disposed on the third dielectric layer and electrically connected to the patterned conductive layer and the active devices. | 06-30-2011 |
20110292331 | PIXEL STRUCTURE AND DISPLAY PANEL HAVING THE SAME - A pixel structure includes a first and a second scan lines, a data line, a first insulating layer covering the first and the second scan lines and a portion of the data line and having a recess, a second insulating layer covering the first insulating layer, a capacitor electrode line covering the data line and the recess, a third insulating layer on the capacitor electrode line, a first active device electrically connected to the second scan line and the data line, a second active device electrically connected to the first active device and the first scan line, and a first and a second pixel electrodes electrically connected to the first and the second active devices, respectively. The portion of the data line and the first and the second scan lines are in the same layer. The recess is located at two sides of the portion of the data line. | 12-01-2011 |
20120161136 | THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor (TFT) array substrate with few processing steps and simple structure is provided, wherein merely two patterned metal layers are required and a patterned planarization layer is adopted to separate the two patterned metal layers from each other and thereby reduce power loading. In addition, the patterned planarization layer has slots to form height differences so as to separate scan lines from common electrodes to further reduce the power loading. | 06-28-2012 |
Ke-Chih Chien, Tucheng City TW
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20120103092 | Temperature and Humidity Measuring Device Deployed on Substrate - The present invention provides a temperature and humidity measuring and recording device deployed on substrate for measuring and recording temperature and humidity of the interior of any station for reticles and of any SMIF POD. The temperature and humidity measuring and recording device comprises a substrate with a first surface and a second surface opposite to the first surface on another side of the substrate, a first measurement unit embedded in and fixed to the first surface of the substrate for measuring the temperature and humidity of the surrounding environment, and a second measurement unit embedded in and fixed to the second surface of the substrate for measuring the temperature and humidity of the interior between the substrate and the pellicle film. | 05-03-2012 |
Ke-Chih Chou, Zhonghe City TW
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20110018609 | TEMPERATURE COMPENSATION IN OUTPUT FEEDBACK OF A FLYBACK POWER CONVERTER - A secondary circuit of a flyback power converter has a resistor network to monitor the output current of the flyback power converter, so as to generate a voltage to apply to a base of a bipolar junction transistor to thereby provide a collector signal for output feedback. The resistor network has a temperature-dependent resistance to compensate the temperature dependence of the base-emitter voltage imparted to the output current and thereby stable the output current. | 01-27-2011 |
Ke-Chih Liu, Hsin-Chu TW
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20130064973 | Chamber Conditioning Method - A system and method for conditioning a chamber is disclosed. An embodiment comprises utilizing the deposition chamber to deposit a first layer and conditioning the deposition chamber. The conditioning the deposition chamber can be performed by depositing a heterogeneous material over the first layer. The heterogeneous material can cover and encapsulate the first layer, thereby preventing particles of the first layer from breaking off and potentially landing on a substrate during a subsequent processing run. | 03-14-2013 |
20130089934 | Material Delivery System and Method - A system and method for controlling saturated vapor pressure of a precursor material is provided. An embodiment comprises generating a calibration curve and utilizing the calibration curve to control a temperature of the precursor material in order to control its saturated vapor pressure. Alternatively, the calibration curve may be substituted for a real time sensor which can take readings in real time and adjust the temperature and saturated vapor pressure based upon the real time readings. | 04-11-2013 |
Ke-Chih Liu, Hsinchu City TW
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20160043186 | SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a gate stack positioned over the semiconductor substrate. The gate stack includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The semiconductor device structure includes spacers positioned over first sidewalls of the gate stack. The spacers and the gate stack surround a recess. The semiconductor device structure includes an insulating layer formed over the semiconductor substrate and surrounding the gate stack. The semiconductor device structure includes a cap layer covering the insulating layer, the spacers, and inner walls of the recess. | 02-11-2016 |