Patent application number | Description | Published |
20100181546 | NONVOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD THEREOF - A nonvolatile semiconductor memory using carbon related films as variable resistance films includes bottom electrodes formed above a substrate, buffer layers formed on the bottom electrodes and each formed of a film containing nitrogen and containing carbon as a main component, variable resistance films formed on the buffer layers and each formed of a film containing carbon as a main component and the electrical resistivity thereof being changed according to application of voltage or supply of current, and top electrodes formed on the variable resistance films. | 07-22-2010 |
20100213433 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon. | 08-26-2010 |
20100237319 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - This nonvolatile semiconductor memory device comprises a memory cell array including memory cells arranged therein. Each of the memory cells is located at respective intersections between first wirings and second wirings and includes a variable resistance element. The variable resistance element comprises a thin film including carbon (C). The thin film includes a side surface along a direction of a current flowing in the memory cell. The side surface includes carbon nitride (CN | 09-23-2010 |
20110049463 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes: a substrate; a first electrode formed on the substrate; a resistance change layer formed on the first electrode, the resistance change layer containing conductive nano-material; a second electrode formed on the resistance change layer; and an insulating buffer layer disposed between the first electrode and the resistance change layer, the insulating buffer layer containing conductive material dispersed therein for assuring the electric conductivity between the first electrode and the resistance change layer. | 03-03-2011 |
20110198556 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device in accordance with an embodiment comprises a lower electrode layer, a variable resistance layer, and an upper electrode layer. The lower electrode layer is provided over a substrate. The variable resistance layer is provided on the lower electrode layer and is configured such that an electrical resistance of the variable resistance layer can be changed. The upper electrode layer is provided on the variable resistance layer. The variable resistance layer comprises a carbon nanostructure and metal atoms. The carbon nanostructure is stacked to have a plurality of gaps. The metal atoms are diffused into the gaps. | 08-18-2011 |
20110235395 | SEMICONDUCTOR MEMORY DEVICE AND WRITING METHOD THEREOF - A memory cell array includes memory transistors each including a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a variable resistance film formed on the gate electrode and made of a variable resistance material having variable resistance and is configured by plural memory strings disposed with longer direction extending in a first direction and including plural series-connected memory transistors. Word lines are disposed with a longer direction extending in a second direction orthogonal to the first direction, and connected commonly to the gate electrodes of the plural memory transistors lined up in the second direction. A plate line is disposed to sandwich the variable resistance film with the gate electrode. First voltage terminals supply a certain voltage to first ends of the plural memory strings. Second voltage terminals supply a certain voltage to second ends of the plural memory strings. | 09-29-2011 |
20120217464 | NONVOLATILE STORAGE DEVICE - A nonvolatile storage device is formed by laminating a plurality of memory cell arrays, the memory cell array including a plurality of word lines, a plurality of bit lines, and memory cells. The memory cell includes a current rectifying device and a variable resistance device, the variable resistance device includes a lower electrode, an upper electrode, and a resistance change layer including a conductive nano material formed between the lower electrode and the upper electrode, one of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the lower electrode serving as a cathode, the other of the variable resistance devices provided adjacent to each other in the laminating direction has titanium oxide (TiOx) between the resistance change layer and the upper electrode serving as a cathode. | 08-30-2012 |
20130248801 | SEMICONDUCTOR MEMORY DEVICE WITH RESISTANCE CHANGE FILM AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of insulating layers, a plurality of first interconnection layers, a plurality of second interconnection layers, a plurality of memory cells, and a resistance change film. The insulating layers and first interconnection layers are arranged in parallel with the semiconductor substrate. The second interconnection layers are arranged so as to intersect the first interconnection layers. The second interconnection layers are arranged perpendicular to the semiconductor substrate. The memory cells are arranged at intersections of the first and second interconnection layers. Each of the memory cells includes the resistance change film arranged between the first and second interconnection layers. The side of the first interconnection layer in contact with the resistance change film is retreated more in a direction to separate from the second interconnection layer than the side of the insulating layer. | 09-26-2013 |
20140016398 | NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes memory cells, each of which is arranged at an intersection between a first wiring and a second wiring intersecting each other. Each of the memory cells includes: a first electrode layer; a plurality of variable resistance layers laminated on the first electrode layer and functioning as variable resistance elements; a second electrode layer formed between the variable resistance layers; and a third electrode layer formed on the top one of the variable resistance layers. Each of the variable resistance layers is composed of a material containing carbon. | 01-16-2014 |
Patent application number | Description | Published |
20090142519 | Ink-Jet Recording Medium - An ink-receiving layer has a bilayer constitution, which is formed by sequentially laminating a lower layer and an upper layer on a support. The upper layer contains alumina having an average pore diameter of less than 5 nm (alumina A) and alumina having an average pore diameter of 5 nm or more (alumina B) in a weight ratio of (alumina A):(alumina B)=100:0 to 70:30; the lower layer contains the alumina A and the alumina B in a weight ratio of (alumina A):(alumina B)=0:100 to 50:50; and the thickness ratio of the upper layer to the lower layer is as follows: (upper layer):(lower layer)=2:1 to 5:1. | 06-04-2009 |
20100034994 | INK-JET RECORDING MEDIUM - An ink-jet recording medium which comprises: a resin-coated paper comprising a base paper and resin layers with which both surfaces of the base paper are coated, respectively; and an ink-receiving layer formed by coating on one of the resin layers, the ink-receiving layer containing an inorganic particle and a binder for the inorganic particle and the inorganic particle being made of alumina, wherein the base paper has a thickness of 100 to 300 μm and the thickness ratio of one of the resin layers that is located between the base paper and the ink-receiving layer to the other resin layer is as follows: (the one resin layer):(the other resin layer)=1:1 to 1:2. | 02-11-2010 |
20100321454 | INKJET RECORDING SHEET - The present invention relates to an inkjet recording sheet for forming an image using aqueous pigment ink comprising: a substrate; and an ink-receiving layer formed on the substrate, wherein the ink-receiving layer is obtained by applying, on the substrate, a coating composition containing: a cationic acrylic silicone emulsion-based resin having a hydrolyzable silyl group as a crosslinking component; a cationic polyether-based urethane resin; and a carbodiimide group-containing resin, followed by curing the applied coating composition, and wherein, in the coating composition, the content of the cationic acrylic silicone emulsion-based resin is 2 to 7% by mass, the content of the cationic polyether-based urethane resin is 88 to 94% by mass, and the content of the carbodiimide group-containing resin is 2 to 6% by mass in terms of solid matter. | 12-23-2010 |
Patent application number | Description | Published |
20110303888 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The memory cell includes a plurality of layers. The plurality of layers includes a carbon-containing memory layer sandwiched between a first electrode film and a second electrode film and a carbon-containing barrier layer provided at least one of between the first electrode film and the memory layer and between the second electrode film and the memory layer. The barrier layer has lower electrical resistivity than the memory layer. | 12-15-2011 |
20110306199 | METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film. | 12-15-2011 |
20110309318 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a first interconnect, a second interconnect and a resistance change layer. The first interconnect extends in a first direction on a major surface of a substrate. The second interconnect extends in a second direction non-parallel to the first direction. The resistance change layer includes a conductive nanomaterial, the resistance change layer located between the first interconnect and the second interconnect and being capable of reversibly changing between a first resistance state and a second resistance state by a voltage applied or a current supplied through the first interconnect and the second interconnect. The resistance change layer has a density varied along a third direction generally perpendicular to the first direction and the second direction. | 12-22-2011 |
20120012805 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a first interconnect, a nanomaterial aggregate layer, and a second interconnect. The nanomaterial aggregate layer is provided on the first interconnect. The nanomaterial aggregate layer includes an aggregation of a plurality of micro conductive bodies. The second interconnect is provided on the nanomaterial aggregate layer. At least a lower portion of the nanomaterial aggregate layer is disposed inside the second interconnect as viewed from above. | 01-19-2012 |
20120025159 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a first conductive member and a second conductive member. The first conductive member extends in a first direction. The second conductive member extends in a second direction intersecting the first direction. A portion of the first conductive member connected to the second conductive member protrudes toward the second conductive member. A resistivity of the first conductive member in the first direction is lower than a resistivity of the first conductive member in a third direction of the protrusion of the first conductive member. A resistance value of the first conductive member in the third direction changes. A resistivity of the second conductive member in the second direction is lower than a resistivity of the second conductive member in the third direction. A resistance value of the second conductive member in the third direction changes. | 02-02-2012 |
20120056145 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide. | 03-08-2012 |
20120097914 | MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a memory device includes a selection element layer, a nanomaterial aggregate layer, and a fine particle. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer has a plurality of micro conductive bodies aggregated with an interposed gap. The fine particle has at least a surface made of silicon oxynitride. The fine particle is dispersed between the micro conductive bodies in one portion of the nanomaterial aggregate layer piercing the nanomaterial aggregate layer in a thickness direction. | 04-26-2012 |
20120104352 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer. | 05-03-2012 |
20120119179 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a nanomaterial aggregate layer of a plurality of fine conductors aggregating via gaps and an insulating material disposed in the gaps. | 05-17-2012 |
20120205609 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a lower electrode layer, a nanomaterial assembly layer, a protective layer and an upper electrode layer. The nanomaterial assembly layer is provided on the lower electrode layer and includes a plurality of fine conductors assembled via a gap. The protective layer is provided on the nanomaterial assembly layer, is conductive, is in contact with the fine conductors, and includes an opening. The upper electrode layer is provided on the protective layer and is in contact with the protective layer. | 08-16-2012 |
20130237008 | METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film. | 09-12-2013 |
20130295743 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide. | 11-07-2013 |
20140147942 | MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer. | 05-29-2014 |
Patent application number | Description | Published |
20130340593 | AUTOMATIC PERFORMANCE TECHNIQUE USING AUDIO WAVEFORM DATA - A plurality of sets of waveform data and switchover position information indicative of, for each of the sets of waveform data, one or more possible switchover positions in the waveform data are prestored, and one set of waveform data is reproduced in accordance with the passage of time. During reproduction of a first set of waveform data, a second set of waveform data is designated at given timing in response to a user's instruction. Control is performed such that the waveform data to be reproduced is switched from the first set of waveform data over to the second set of waveform data in response to waveform data reproduction timing arriving at one of the possible switchover positions indicated by the switchover position information corresponding to the second set of waveform data. Reproduction of the second set of waveform data is started at the switchover position corresponding to the reproduction timing. | 12-26-2013 |
20130340594 | AUTOMATIC PERFORMANCE TECHNIQUE USING AUDIO WAVEFORM DATA - Waveform data are stored in advance together with reference position information indicative of reference positions, in the waveform data, corresponding to reference timing, such as beat timing, and correction position information indicative of correction positions in the waveform data that are different from the reference positions. The reference timing is advanced when the waveform data are reproduced. In response to arrival of the reference timing, a deviation between a reproduction position of the currently reproduced waveform data and the reference position is evaluated. When the reproduction position arrives at the correction position, the reproduction position is corrected according to the evaluated deviation. Namely, whereas measurement of the deviation, relative to the reference timing, of the currently reproduced waveform data is performed on the basis of the reference position, correction of the current reproduction position of the waveform data for compensating for the measured deviation is performed at the correction position. | 12-26-2013 |
20160034446 | ESTIMATION OF TARGET CHARACTER TRAIN - A desired character train included in a predefined reference character train, such as lyrics, is set as a target character train, and a user designates a target phoneme train that is indirectly representative of the target character train by use of a limited plurality of kinds of particular phonemes, such as vowels and a particular consonants. A reference phoneme train indirectly representative of the reference character train by use of the particular phonemes is prepared in advance. Based on a comparison between the target phoneme train and the reference phoneme train, a sequence of the particular phonemes in the reference phoneme train that matches the target phoneme train is identified, and a character sequence in the reference character train that corresponds to the identified sequence of the particular phonemes is identified. The thus-identified character sequence estimates the target character train. | 02-04-2016 |