Patent application number | Description | Published |
20140286086 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address. | 09-25-2014 |
20140286087 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command. | 09-25-2014 |
20150109855 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a buffer configured to hold data input to an input/output circuit and to hold data read from the memory cell array, and a controller configured to receive a first command and an address from the outside and to read data, in response to the first command, from a memory cell group coupled to a selected word line designated by the address to the buffer. The controller receives a second command which is input after the first command and indicates a last command of a group of commands including write commands and/or read commands, and starts a write operation from the buffer to the memory cell array in response to the second command. | 04-23-2015 |
20150261602 | RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory comprises a memory cell array, an error checking and correcting (ECC) circuit and a controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The error checking and correcting (ECC) circuit performs an ECC operation to detect an error in data read from the memory cells and correct the error. The controller performs the ECC operation by the ECC circuit at a predetermined period. | 09-17-2015 |
20150262639 | RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory comprises a memory cell array, a write and read circuit, a temperature sensor, and a memory controller. The memory cell array comprises memory cells including magnetic tunnel junction (MTJ) elements. The write and read circuit performs a write operation and a read operation for the memory cells. The temperature sensor outputs temperature information corresponding to a temperature of the memory cell array. The memory controller controls the write operation and the read operation by the write and read circuit in accordance with the temperature information. | 09-17-2015 |
20150318061 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address. | 11-05-2015 |
20160071567 | RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory includes a memory cell, a reference voltage generating circuit, a first transistor and a sense amplifier. The memory cell includes a resistance change element. The reference voltage generating circuit generates a reference adjustment voltage. The first transistor provides a reference current in accordance with the reference adjustment voltage. The sense amplifier compares a cell current flowing through the memory cell with the reference current flowing through the first transistor. | 03-10-2016 |
20160133308 | RESISTANCE CHANGE MEMORY - A resistance change memory includes a memory cell array comprising memory cells including magnetic tunnel junction (MTJ) elements; a write and read circuit which performs a write operation and a read operation for the memory cells; a temperature sensor which outputs temperature information corresponding to a temperature of the memory cell array; and a memory controller which controls the write operation and the read operation by the write and read circuit in response to the temperature information, such that a first time period from a write command input to a pre-charge command input is variable according to the temperature information, while a second time period from an active command input to the pre-charge command input is fixed constant regardless of the temperature information. | 05-12-2016 |