Patent application number | Description | Published |
20100166130 | Phase Locked Loop with Optimal State Feedback Controller - In a method of recovering timing information over a packet network at a local receiver, timing information is received at intervals timing from a remote source and compared with a locally generated clock signal to generate an input signal y(k) subject to noise representative of the phase difference between the source clock signal and the local receiver clock signal. The input signal is applied to a state feedback controller, preferably including a Kalman filter, to generate a control signal with reduced noise. The control signal is used to control an oscillator in a way so as to reduce the phase difference and generate a slave clock. | 07-01-2010 |
20100296406 | TIMING RECOVERY OVER PACKET NETWORKS - In a method of recovering timing information over packet networks, raw network delays are measured using timing packets sent between a transmitter and receiver. The expected delay is predicted using a minimum statistics adaptive filter to track local minima of measured time delays over a smoothing window. Only those incoming timing packets which meet a particular criterion relative to the expected delay within a smoothing window are selected, and a local clock is adjusted based on the measured timing delays from the selected timing packets. | 11-25-2010 |
20100296524 | MULTI INPUT TIMING RECOVERY OVER PACKET NETWORK - In a method of recovering timing information over packet networks, a receiver receives a plurality of packet streams over different paths from the same source. The raw delays experienced by the timing packets for each stream are filtered to provide a filtered delay for each stream. The filtered delays are weighted based on the quality of each stream, and the weighted filtered delays are then combined to form an aggregate delay estimate. Frequency adjustments for a local clock at the receiver are derived from the aggregate delay estimate. | 11-25-2010 |
20110194438 | Clock Recovery Method over Packet Switched Networks based on Network Quiet Period Detection - A method of recovering timing information in a packet network, involves detecting quiet periods in the packet network when network packet delay variation (PDV) is low. A frequency prediction unit is trained during the quiet periods to learn output clock variations of a timing recovery unit to permit the frequency prediction unit to predict frequency update values for a local oscillator during non quiet periods taking into account the historical output clock variations during quiet periods. The output of the frequency prediction unit is used as the active frequency update values during non quiet periods. | 08-11-2011 |
20120154610 | MOTOR NOISE REDUCTION CIRCUIT - A method of reducing noise in an environment where the noise source is in a fixed location relative to a pair of microphones, such as in a camera with a zoom motor, involves receiving signals x | 06-21-2012 |
20140320186 | PHASE LOCKED LOOP WITH PRECISE PHASE AND FREQUENCY SLOPE LIMITER - Phase slope is controlled in a phase locked loop wherein a phase error signal controlling a controlled oscillator has a proportional component and an integral component, by determining whether the proportional component falls within a range bounded by upper and lower limit values. The proportional component is combined with the integral component if the proportional component falls within the range to provide the phase error signal. Otherwise, the proportional component is modified to meet a phase slope requirement while leaving the integral component unmodified. The modified proportional component is combined with the unmodified integral component to provide the phase error signal. | 10-30-2014 |
20150200770 | NETWORK INTERFACE WITH CLOCK RECOVERY MODULE ON LINE CARD - A network interface for recovering timing information over packet networks has line card at the edge of a local network and a timing card separate from the line card. A physical interface time-stamps incoming timing packets based on smoothed recovered clock signals. A clock recovery module on the line card generates timing signals from the time-stamped incoming timing packets. A first phase locked generates raw clock signals from the timing signals. A second phase locked loop on the timing card generates the smoothed clock signals from said raw clock signals and applies them to the clock recovery module on the line card. | 07-16-2015 |
20150326232 | Crystal Oscillator Noise Compensation Method for a Multi-Loop PLL - A multi-loop phase locked loop (PLL) system with noise attenuation has a first PLL including a local oscillator, a second PLL coupled to an output of the first PLL, and a third PLL in a feedback path between the second PLL and first PLL. A first phase comparator compares an input signal with the first feedback signal to generate a first phase error signal for the first PLL. The first phase error signal is multiplied by a scaling factor k determining the amount of noise attenuation. The third PLL has a bandwidth preferably at least ten times higher than the second PLL so that the overall transfer function of the second and third PLLs is approximately the transfer function of the second PLL. The transfer function of the third PLL is multiplied by a scaling factor 1/k. This arrangement allows the use of an uncompensated local oscillator in the first PLL. The noise generated in the uncompensated local oscillator is reduced by the attenuation factor k. | 11-12-2015 |