Patent application number | Description | Published |
20090108769 | LIGHTING DEVICE AND ILLUMINATION APPARATUS - The present invention provides a lighting device capable of controlling finely modulated light control without stopping other processing regardless of an operation clock. The light modulation signal generating portion calculates a cycle of a PWM signal based on the lighting state of lamp, which is detected by state detecting portion and a predetermined operation clock. A PWM signal of the cycle calculated by the state detecting portion is generated by the light modulation signal generating portion capable of generating the PWM signal corresponding to the cycle of a non-integral number of times of the operation clock, wherein the cycle of the PWM signal can be continuously and finely varied without stopping other processing regardless of operation clocks, and fine modulated light control is enabled. | 04-30-2009 |
20090134813 | DISCHARGE LAMP LIGHTING DEVICE - The inverter circuit is feedback-controlled by a substantial current flowing into the discharge lamp, which is detected by the current detecting means. A high starting voltage is supplied to the discharge lamp with the operation frequency lowered by the control circuit after the end of a preheating action. The inverter circuit is controlled so that the current of the discharge lamp becomes a desired current value as soon as the current detecting means detects the current substantially flowing into the discharge lamp. The discharge lamp can be prevented from being instantaneously brightly lit without separately providing any structure for detecting lighting of the discharge lamp. | 05-28-2009 |
20100097007 | LIGHT-EMITTING DIODE LIGHTING DEVICE - There is provided an LED lighting device having a satisfactory temperature characteristic and a small amount of variation in output current. The step-down chopper is provided with a first circuit including the switching element, the impedance means and a first inductor connected in series and a second circuit including the first inductor and a diode connected in series. A self-excited drive signal generation circuit is provided with a second inductor magnetically coupled with the first inductor and applies a voltage induced in the second inductor to the switching element to keep the switching element on. A turn-off circuit outputs an output voltage when the voltage of the impedance means detected by a comparator exceeds the reference value, and the output voltage allows a switching element to turn on to short-circuit the output terminals of the self-excited drive signal generation circuit, resulting in that the switching element is turned off. | 04-22-2010 |
Patent application number | Description | Published |
20090000731 | HERMETICALLY SEALED CONTAINER AND MANUFACTURING METHOD OF IMAGE FORMING APPARATUS USING THE SAME - A manufacturing method of a hermetically sealed container, comprises steps of placing, on a first member, a first bonding material and a second bonding material having a larger compressibility in relation to a pressing force than a compressibility of the first bonding material, such that the first and second bonding materials are arranged side-to-side relationship, and the first bonding material has a height lower than a height of the second bonding material; pressing a second member to the second bonding material; heating and melting sequentially part by part the first bonding material; and cooling the first bonding material to bond together the first and second members. | 01-01-2009 |
20090205849 | HERMETIC ENVELOPE AND IMAGE DISPLAY APPARATUS USING THE SAME - A hermetic envelope includes a first plate, a second plate, and a frame provided between the first plate and the second plate to form an interior space. A first bonding part is provided between the frame and the first plate to bond the frame and the first plate to each other, and a first abutting part is provided between the frame and the first plate, and positioned closer to the interior space than the first bonding part. A second bonding part is provided between the frame and the second plate to bond the frame and the second plate to each other, and a second abutting part is provided between the frame and the second plate and positioned closer to the interior space than the second bonding part. The second bonding part is positioned closer to the interior space than the first bonding part. | 08-20-2009 |
20100035507 | MANUFACTURING METHOD OF IMAGE DISPLAY APPARATUS - There is provided a manufacturing method of an image display apparatus for activating getters so as to exhibit higher exhaust performance after sealing of a vacuum container. In an exhaust process for exhausting inner gas from an exhaust hole, activation is performed by local heating sequentially from the getters positioned in a region where an exhaust conductance is larger with respect to the exhaust hole. | 02-11-2010 |
Patent application number | Description | Published |
20110296008 | IMAGE PROCESSING APPARATUS, INFORMATION PROCESSING APPARATUS, AND METHOD THEREFOR - An image processing apparatus capable of requesting a service providing apparatus via an external network to perform processing and communicating with an information processing apparatus via an internal network includes an activation unit configured to activate a check unit configured to check a status of the processing acquired by the information processing apparatus, a stopping unit configured to stop the check unit if the check unit activated by the activation unit recognizes that the status of the processing is not a stopped state, and a request unit configured to request the service providing apparatus to perform the processing if the check unit is stopped. | 12-01-2011 |
20120194837 | SYSTEM, IMAGE FORMING APPARATUS, AND METHOD - Information about a user is sent to a server from a device to perform authentication. A scan document generated by scanning a paper document is sent to the server from the device to request registration thereof. If the scan document, the registration of which has been requested from the device, has a size that exceeds free space in a contract area, the server extracts a document that meets a save condition from documents that should be stored in the contract area. The server then moves the extracted document from the contract area into a temporary area so as to register in the contract area the scan document the registration of which has been requested from the device. The server notifies a predetermined destination of information about the document moved into the temporary area. | 08-02-2012 |
20130326324 | DOCUMENT MANAGEMENT SERVER, DOCUMENT MANAGEMENT METHOD, AND STORAGE MEDIUM - A document management server, in a case where a document of the same name as that of a document being requested to be registered from a client has been registered, determines whether the document of the same name has a plurality of versions. If the document management server determines that the document of the same name has a plurality of versions, after the document name of the document of the same name has been changed, the document management server registers the document being requested to be registered. Meanwhile, if the document management server determines that the document of the same name has only one version, the document management server overwrites the document being requested to be registered with the document of the same name, and registers the overwritten document. | 12-05-2013 |
Patent application number | Description | Published |
20080253195 | SEMICONDUCTOR MEMORY DEVICE WHICH INCLUDES MOS TRANSISTOR HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA READOUT METHOD THEREOF - A semiconductor memory device includes first and second memory cells and a sense amplifier. The first memory cell includes a MOS transistor and is capable of retaining n-bit (n is a natural number more than one) first data. The MOS transistor includes a charge accumulation layer and a control gate. The second memory cell retains second data. The second data is a criterion for the first data. The sense amplifier determines the first data read out from the first memory cell and amplifies the first data using a first reference level and a second reference level. The first reference level is obtained based on the second data read out from the second memory cell. The second reference level is generated inside based on the first reference level. | 10-16-2008 |
20090115500 | VOLTAGE GENERATING CIRCUIT - A voltage generating circuit for outputting a voltage from an output terminal, has a first voltage dividing circuit which is connected between the output terminal and ground; a switch circuit connected between the output terminal and the first voltage dividing circuit; a first voltage detecting circuit which outputs a first pumping signal corresponding to a comparison result; a second voltage dividing circuit which is connected between the output terminal and the ground; a second voltage detecting circuit which outputs a second pumping signal corresponding to a comparison result; a pump circuit that outputs a voltage boosted from a power supply voltage; and a boost circuit which has a capacitive element having one end connected to the voltage dividing resistor of the first voltage dividing circuit. | 05-07-2009 |
20090129148 | SEMICONDUCTOR MEMORY - A semiconductor memory capable of storing and reading data in a memory cell for holding the data corresponding to a threshold voltage has a reference current generating circuit having a reference current generating section and an amplifier section. | 05-21-2009 |
20090135657 | SEMICONDUCTOR MEMORY - A semiconductor memory has a first-stage amplifier circuit, wherein data stored in a memory cells is read based on a potential between an amplifier input MOS transistor and an amplifier reference MOS transistor, the potential being outputted from the first-stage amplifier circuit. | 05-28-2009 |
20100214837 | NONVOLATILE SEMICONDUCTOR MEMORY WITH CHARGE STORAGE LAYERS AND CONTROL GATES - A nonvolatile semiconductor memory includes a memory cell array, bit lines, a first voltage generator, and a second voltage generator. The memory cell array includes memory cells. The bit lines each of which is connected electrically to one end of the current path of the corresponding one of the memory cells. The first voltage generator which is capable of supplying via a first output terminal to the bit lines a first voltage externally supplied or a third voltage which is obtained by stepping down a second voltage supplied and higher than the first voltage and which is as high as the first voltage. The second voltage generator which is capable of supplying a fourth voltage obtained by stepping down the second voltage to the bit lines via a second output terminal when the first voltage generator steps down the second voltage to generate the third voltage. | 08-26-2010 |
20100238736 | Semiconductor storage device - 1. A semiconductor storage device has a first MOS transistor connected at a first end thereof to a power supply and diode-connected; a second MOS transistor connected in parallel with the first MOS transistor; a memory cell connected between the second end of the first MOS transistor and ground, the memory cell capable of adjusting a current flowing through the memory cell; a third MOS transistor connected at a first end thereof to the power supply, and diode-connected; a fourth MOS transistor connected in parallel with the third MOS transistor; a fifth MOS transistor connected between the second end of the fourth MOS transistor and the ground and supplied at a gate thereof with the first reference voltage; and an amplifier circuit which compares the sense voltage with the comparison voltage, and which outputs a comparison result signal depending upon a result of the comparison. | 09-23-2010 |
20120069683 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a semiconductor storage device includes a cell array, an even line, an odd line, and sense amplifiers. The cell array includes memory cells holding data. The even line connects to the memory cells. The odd line connects to the memory cells. The memory cells connect to an odd column or the even column. Each the sense amplifiers selectively connect to the odd line or the even line. Each the sense amplifiers includes a latch circuit, a first transistor, a second transistor, and a third transistor. The latch circuit includes a first node and a second node, and holds the data supplied to the first node. The first transistor supplies read data to the latch circuit. The second transistor transfers the data held by the latch circuit to the wiring. The third transistor transfers the data held by the latch circuit to the wiring. | 03-22-2012 |
20120113724 | SEMICONDUCTOR MEMORY - According to one embodiment, a semiconductor memory includes a memory cell array including a plurality of memory cells, a sense amplifier circuit holding a verification result for the memory cells and including sense units, the sense units of each column block being connected in common to a first signal line, and a detecting circuit including a detecting unit. The detecting unit includes a first latch circuit which holds failure information in the memory cell arrays, and a second latch circuit which includes a first input terminal connected to the first signal line, a second input terminal connected to the first latch circuit, and a first output terminal connected to a second signal line. | 05-10-2012 |
20130279254 | SEMICONDUCTOR MEMORY STORAGE APPARATUS HAVING CHARGE STORAGE LAYER AND CONTROL GATE - According to one embodiment, a semiconductor memory storage apparatus includes an array, a sense amplifier, and a controller. The array includes a memory cell. The sense amplifier includes a first latch and a second latch. The first latch and the second latch are capable of storing a data read out from the memory cell. The controller performs a first operation, a second operation, and a third operation. In the first operation, the controller transfers an inverted data in the first latch to the first node and transfers the data in the second latch. In the second operation, the controller transfers the data in the first latch to the first node and transfers an inverted data in the second latch. | 10-24-2013 |
20130279255 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR CONTROLLING THE SAME - According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line. | 10-24-2013 |
20130286738 | SEMICONDUCTOR MEMORY APPARATUS - According to one embodiment, a semiconductor memory apparatus includes an array, a source, a bit line, a sense, and current circuit. The array includes a NAND string. The NAND string includes memory cell. The sense includes a first transistor. One end of transistor is connected to a first node, and other end of the transistor is connected to a second. The first node is used for reading the data held by the memory cell. An internal voltage is smaller than the source voltage. The current circuit outputs a first voltage to a gate of the transistor, and the first voltage is smaller than the internal voltage. The transistor limits a first current from the source to the sense based on a threshold voltage of the memory cell to be read. | 10-31-2013 |