Patent application number | Description | Published |
20090278757 | MOBILE TERMINAL HAVING METAL CASE AND ANTENNA STRUCTURE - A mobile terminal including a metal case and an antenna structure that can exhibit optimum radiation performance is provided. The antenna structure includes an antenna having a radiation unit for transmitting and for receiving electric waves, a Printed Circuit Board (PCB) to which the antenna is mechanically coupled at one surface thereof and having a power supply unit electrically coupled to the radiation unit, and a case constructed using a metal material within which the PCB is disposed, wherein the case has at least one slot formed in a surface thereof opposite to the surface to which the PCB is fastened and adjacent to the radiation unit. | 11-12-2009 |
20110037665 | MULTIBAND BUILT-IN ANTENNA FOR PORTABLE TERMINAL - A multiband built-in antenna of a portable terminal is provided. The multiband built-in antenna includes a main board having a ground area and a non-ground area on a front surface and an opposite surface, and an antenna radiator having a specific pattern directly formed on the non-ground area of the main board, wherein the antenna radiator comprises a first antenna radiator of which one end is branched off into two parts on the front surface of the main board so that one part is used for feeding and the other part is electrically connected to the ground area, and of which the other end is extended by a specific length in a widthwise direction of the terminal, and a second antenna radiator which protrudes towards the opposite surface of the main board from the other end of the first antenna radiator and is formed in a specific pattern in the non-ground area on the opposite surface of the main board. | 02-17-2011 |
20110085561 | Incremental Adaptive Packet Routing In A Multi-Dimensional Network - Illustrated is a computer system and method that includes a Processing Element (PE) to generate a data packet that is routed along a shortest path that includes a plurality of routers in a multiple dimension network. The system and method further include a router, of the plurality of routers, to de-route the data packet from the shortest path to an additional path, the de-route to occur where the shortest path is congested and the additional path links the router and an additional router in a dimension of the multiple dimension network. | 04-14-2011 |
20120020242 | METHODS AND APPARATUS TO DETERMINE AND IMPLEMENT MULTIDIMENSIONAL NETWORK TOPOLOGIES - Methods and apparatus to determine and implement multidimensional network topologies are disclosed. An example method disclosed herein comprises receiving an input parameter for determining a multidimensional network topology for a network interconnecting a plurality of devices, and determining a set of multidimensional network topologies, each multidimensional network topology of the set comprising a respective plurality of nodes to interconnect the plurality of devices, each node in each multidimensional network topology of the set being fully connected with all neighbor nodes in each dimension of the multidimensional network topology, and each multidimensional network topology of the set satisfying a first constraint based on the input parameter. | 01-26-2012 |
20120189026 | TUNABLE RESONATORS - Various embodiments of the present invention relate to electronically tunable ring resonators. In one embodiment of the present invention, a resonator structure ( | 07-26-2012 |
20140268978 | SEMICONDUCTOR MEMORY DEVICE HAVING ASYMMETRIC ACCESS TIME - A semiconductor memory device may include a plurality of data input/output DQ pads and a plurality of first and second memory cell arrays. Each path of a first set of data paths from each of the plurality of first memory cell arrays to a corresponding DQ pad is physically shorter than each path of a second set of data paths from each of the plurality of second memory cell arrays to the corresponding DQ pad. Each of the plurality of first memory cell arrays is a designated first-speed access cell array and each of the plurality of second memory cell arrays is a designated second-speed access cell array, the second-speed being slower than the first-speed. A size of the each of the plurality of first memory cell arrays is smaller than a size of the each of the plurality of second memory cell arrays. | 09-18-2014 |
Patent application number | Description | Published |
20090103345 | Three-dimensional memory module architectures - Various embodiments of the present invention are directed to stacked memory modules. In one embodiment of the present invention, a memory module comprises at least one memory-controller layer stacked with at least one memory layer. Fine pitched through vias (e.g., through silicon vias) extend approximately perpendicular to a surface of the at least one memory controller through the stack providing electronic communication between the at least one memory controller and the at least one memory layers. Additionally, the memory-controller layer includes at least one external interface configured to transmit data to and from the memory module. Furthermore, the memory module can include an optical layer. The optical layer can be included in the stack and has a bus waveguide to transmit data to and from the at least one memory controller. The external interface can be an optical external interface which interfaces with the optical layer. | 04-23-2009 |
20090103929 | Synchronous optical bus providing communication between computer system components - A synchronous optical bus system for communication between computer system components is described. In one example, the optical bus system is used for communication between a memory controller and memory devices optically coupled to an optical interconnect. Optical bus interface units couple the components to the optical interconnect and are arranged on the optical interconnect in order that a sum of an optical path length from a controller component to each computer system component and from each computer system component to the controller component is the same for all the coupled computer system components. A synchronous protocol is used for communication between the components. | 04-23-2009 |
20110052204 | Intentionally Skewed Optical Clock Signal Distribution - Embodiments of the present invention relate to systems and methods for distributing an intentionally skewed optical-clock signal to nodes of a source synchronous computer system. In one system embodiment, a source synchronous system comprises a waveguide, an optical-system clock optically coupled to the waveguide, and a number of nodes optically coupled to the waveguide. The optical-system clock generates and injects a master optical-clock signal into the waveguide. The master optical-clock signal acquiring a skew as it passes between nodes. Each node extracts a portion of the master optical-clock signal and processes optical signals using the portion of the master optical-clock signal having a different skew for the respective extracting node. | 03-03-2011 |
20110069963 | Optoelectronic Switches Using On-chip Optical Waveguides - Embodiments of the present invention are directed to optoelectronic network switches. In one embodiment, an optoelectronic switch includes a set of roughly parallel input waveguides and a set of roughly parallel output waveguides positioned roughly perpendicular to the input waveguides. Each of the output waveguides crosses the set of input waveguides. The optoelectronic switch includes at least one switch element configured to switch one or more optical signals transmitted on one or more input waveguides onto one or more crossing output waveguides. | 03-24-2011 |
20110145493 | Independently Controlled Virtual Memory Devices In Memory Modules - Various embodiments of the present invention are directed a multi-core memory modules. In one embodiment, a memory module ( | 06-16-2011 |
20120011349 | DATA EXCHANGE AND COMMUNICATION BETWEEN EXECUTION UNITS IN A PARALLEL PROCESSOR - Disclosed are methods and systems for dynamically determining data-transfer paths. The data-transfer pats are determined in response to an instruction that facilitates data transfer among execution lanes in an integrated-circuit processing device operable to execute operations in parallel. | 01-12-2012 |
Patent application number | Description | Published |
20080315354 | FUSE FOR SEMICONDUCTOR DEVICE - Embodiments relate to a fuse for a semiconductor device. To maintain a stable blowing characteristic with a minimized applied current, the fuse includes a fuse line having a blowing characteristic dependent on applied current. A first contact pad has a plurality of contacts connected to one side of the fuse line. A second contact pad has a plurality of contacts connected to the other side of the fuse line. The first and second contact pads have an asymmetrical configuration, which may have different ratios of length to width. | 12-25-2008 |
20090057782 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. Embodiments relate to a semiconductor device which includes an active region including a source region, a drain region, and a channel region. A gate electrode, source electrodes, and a drain electrode are formed around the active region. A plurality of gate fingers diverge from the gate electrode into the channel region. A plurality of source fingers diverge from the source electrodes into the source region, the source fingers being disposed between the gate fingers in a predetermined pattern, the source fingers having at least two finger lines connected to each other via at least one grid line. A plurality of drain fingers diverge from the drain electrode into the drain region, the drain fingers being disposed between the gate fingers where the source fingers are not disposed. | 03-05-2009 |
20090186461 | Narrow Width Metal Oxide Semiconductor Transistor - Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W | 07-23-2009 |