Patent application number | Description | Published |
20150320189 | Adapter for Attaching a Motion Capture Device to a Head Mounted Display - The technology disclosed relates to providing devices and methods for attaching motion capture devices to head mounted displays (HMDs) using existing features of the HMDS, with no modification to the design of the HMDs. A motion capture device is attached with an adapter to a wearable device that can be a personal HMD having a goggle form factor. The motion capture device is operable to be attached to or detached from an adapter, and the adapter is operable to be attached to or detached from an HMD. The motion capture device is attached to the HMD with an adapter in a fixed position and orientation. In embodiments, the attachment mechanism coupling the adapter to the HMD utilizes existing functional or ornamental elements of an HMD. Functional or ornamental elements of the HMD include; air vents, bosses, grooves, recessed channels, slots formed where two parts connect, openings for head straps etc. | 11-12-2015 |
20150326762 | Mounts for Attaching a Motion Capture Device to a Head Mounted Display - The technology disclosed relates to providing devices and methods for attaching motion capture devices to head mounted displays (HMDs) using existing features of the HMDS, with no modification to the design of the HMDs. A motion capture device is attached with an adapter to a wearable device that can be a personal HMD having a goggle form factor. The motion capture device is operable to be attached to or detached from an adapter, and the adapter is operable to be attached to or detached from an HMD. The motion capture device is attached to the HMD with an adapter in a fixed position and orientation. In embodiments, the attachment mechanism coupling the adapter to the HMD utilizes existing functional or ornamental elements of an HMD. Functional or ornamental elements of the HMD include; air vents, bosses, grooves, recessed channels, slots formed where two parts connect, openings for head straps etc. | 11-12-2015 |
Patent application number | Description | Published |
20080268630 | METHOD TO OBTAIN MULTIPLE GATE THICKNESSES USING IN-SITU GATE ETCH MASK APPROACH - Making gates having multiple thicknesses on the same substrate in a given process flow is provided. For example, a method of making a semiconductor structure having at least two gates of different thickness involves forming a first gate layer having a first thickness; patterning a first hard mask over a portion of the first gate layer to define a first gate underneath the first hard mask having a first gate thickness; forming a second gate layer having a second thickness over the first gate layer and the first hard mask; patterning a second hard mask over a portion of the second gate layer to define a second gate underneath the second hard mask having a second gate thickness; removing portions of the first gate layer and the second gate layer that are not under the first hard mask and the second hard mask; and removing the first hard mask and the second hard mask to provide two gates of different thicknesses. | 10-30-2008 |
20110176363 | JUNCTION LEAKAGE SUPPRESSION IN MEMORY DEVICES - A memory device includes a substrate and source and drain regions formed in the substrate. The source and drain regions include both phosphorous and arsenic and the phosphorous may be implanted prior to the arsenic. The memory device also includes a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may further include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. | 07-21-2011 |
20120228704 | High-Voltage MOSFET with High Breakdown Voltage and Low On-Resistance and Method of Manufacturing the Same - A high-voltage transistor is formed in a deep well of a first conductivity type that has been formed in a semiconductor substrate or epitaxial layer of a second conductivity type. A body region of the second conductivity type is formed in the deep well, into which a source region of the first conductivity type is formed. A drain region of the first conductivity type is formed in the deep well and separated from the body region by a drift region in the deep well. A gate dielectric layer is formed over the body region, and a first polysilicon layer formed over the gate dielectric layer embodies the gate of the transistor. The field plate dielectric layer is formed over the drift region after the gate has been formed. Finally, the field plate dielectric is covered by a second polysilicon layer having a field plate positioned over the field plate dielectric layer in the drift region. | 09-13-2012 |
20140038378 | APPARATUS AND METHOD FOR A METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SOURCE SIDE PUNCH-THROUGH PROTECTION IMPLANT - A metal oxide semiconductor field effect transistor (MOSFET) with source side punch-through protection implant. Specifically, the MOSFET comprises a semiconductor substrate, a gate stack formed above the semiconductor substrate, source and drain regions, and a protection implant. The semiconductor substrate comprises a first p-type doping concentration. The source and drain regions comprise an n-type doping concentration, and are formed on opposing sides of the gate stack in the semiconductor substrate. The protection implant comprises a second p-type doping concentration, and is formed in the semiconductor substrate under the source region and surrounds the source region in order to protect the source region from the depletion region corresponding to the drain region. | 02-06-2014 |
Patent application number | Description | Published |
20090133023 | High Performance Queue Implementations in Multiprocessor Systems - Systems and methods provide a single reader single writer (SRSW) queue structure having entries that can be concurrently accessed in an atomic manner with a single memory access. The SRSW queues may be combined to create more complicated queues, including multiple reader single writer (MRSW), single reader multiple writer (SRMW), and multiple reader multiple writer (MRMW) queues. | 05-21-2009 |
20100250854 | METHOD AND SYSTEM FOR DATA PREFETCHING FOR LOOPS BASED ON LINEAR INDUCTION EXPRESSIONS - An efficient and effective compiler data prefetching technique is disclosed in which memory accesses may be prefetched are represented in linear induction expressions. Furthermore, indirect memory accesses indexed by other memory accesses of linear induction expressions in scalar loops may be prefetched. | 09-30-2010 |
20110047534 | PROACTIVE LOOP FUSION OF NON-ADJACENT LOOPS WITH INTERVENING CONTROL FLOW INSTRUCTIONS - A system and method for optimization of code with non-adjacent loops. A compiler builds a node tree, which is not a control flow graph, that represents parent-child relationships of nodes of a computer program. Each node represents a control flow statement or a straight-line block of statements of the computer program. If a non-adjacent loop pair of nodes satisfy predetermined conditions, the compiler may perform legal code transformations on the computer program and corresponding node transformations on the node tree. These transformations may make adjacent this pair of loop nodes. The compiler may be configured to perform legal code transformations, such as head and tail duplication, code motion, and if-merging, in order to make adjacent these two loop nodes. Then loop fusion may be performed on this loop pair in order to increase instruction level parallelism (ILP) within an optimized version of the original source code. | 02-24-2011 |
20120297163 | AUTOMATIC KERNEL MIGRATION FOR HETEROGENEOUS CORES - A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a program migrates at a given location to a different processor core. The compiler creates a data structure to support moving live values associated with the execution of the function call at the given location. An operating system (OS) scheduler schedules at least code before the given location in program order to the first processor core. In response to receiving an indication that a condition for migration is satisfied, the OS scheduler moves the live values to a location indicated by the data structure for access by the second processor core and schedules code after the given location to the second processor core. | 11-22-2012 |
20130125100 | COMPUTER SYSTEM AND METHOD FOR COMPILING PROGRAM CODE AND ASSIGNING ADDRESS SPACES - A computer system is provided for compiling program code and a method for compiling program code by a processor. The method, for example, includes, but is not limited to, receiving, by the processor, the program code and compiling, by the processor, the program code, wherein the processor, when compiling the program code, parses the program code and assigns a default address space qualifier to each member functions without a defined address space qualifier and, when the member function is used, infers an address space for each default address qualifier based upon how the respective member function is being used. | 05-16-2013 |
20130159685 | CONTROL FLOW-BASED APPROACH IN IMPLEMENTING EXCEPTION HANDLING ON A GRAPHICS PROCESSING UNIT - A function in source code is processed by a compiler for execution on a graphics processing unit, wherein the function includes an exception handling structure. An exception raising block is converted into a first control flow and an exception handler block is converted into a second control flow. The first control flow includes setting an exception raised indicator and finding an exception handler to process the raised exception. The exception raised indicator remains set until an appropriate exception handler is found. The second control flow includes clearing the exception raised indicator and processing the exception. | 06-20-2013 |
Patent application number | Description | Published |
20090109975 | SEPARATION OF DATA AND CONTROL IN A SWITCHING DEVICE - A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path. | 04-30-2009 |
20090268740 | MEMORY ORGANIZATION IN A SWITCHING DEVICE - A network device switches variable length data units from a source to a destination in a network. An input port receives the variable length data unit and a divider divides the variable length data unit into uniform length data units for temporary storage in the network device. A distributed memory includes a plurality of physically separated memory banks addressable using a single virtual address space and an input switch streams the uniform length data units across the memory banks based on the virtual address space. The network device further includes an output switch for extracting the uniform length data units from the distributed memory by using addresses of the uniform length data units within the virtual address space. The output switch reassembles the uniform length data units to reconstruct the variable length data unit. An output port receives the variable length data unit and transfers the variable length data unit to the destination. | 10-29-2009 |
20100165870 | BANDWIDTH DIVISION FOR PACKET PROCESSING - A bandwidth divider and method for allocating bandwidth between a plurality of packet processors. The bandwidth divider includes a plurality of counters for measuring the bandwidth of data packets transferred from the bandwidth divider to a respective packet processor; and a controller for analyzing the plurality of counters and transferring a data packet to a selected packet processor based on the contents of the counters. The method monitors the bandwidth consumed by the packet processors; determines, based on the bandwidth consumed by the packet processors, which packet processor has consumed the least amount of bandwidth; and allocates a next data packet to the packet processor which has consumed the least amount of bandwidth. | 07-01-2010 |
20100177777 | PRESERVING THE ORDER OF PACKETS THROUGH A DEVICE - A network device includes one or more sprayers, multiple packet processors, and one or more desprayers. The sprayers receive packets on at least one incoming packet stream and distribute the packets according to a load balancing scheme that balances the number of bytes of packet data that is given to each of the packet processors. The packet processors receive the packets from the sprayers and process the packets to determine routing information for the packets. The desprayers receive the processed packets from the packet processors and transmit the packets on at least one outgoing packet stream based on the routing information. | 07-15-2010 |
20100309916 | IN-LINE PACKET PROCESSING - A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router. | 12-09-2010 |
20110164618 | MEMORY ORGANIZATION IN A SWITCHING DEVICE - A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking information for each data packet to allow for the extraction of the uniform portions of a data packet from distributed locations in memory in proper order after a routing determination has been made by the router. | 07-07-2011 |
20110235642 | PRESERVING THE ORDER OF PACKETS THROUGH A DEVICE - A network device includes one or more sprayers, multiple packet processors, and one or more desprayers. The sprayers receive packets on at least one incoming packet stream and distribute the packets according to a load balancing scheme that balances the number of bytes of packet data that is given to each of the packet processors. The packet processors receive the packets from the sprayers and process the packets to determine routing information for the packets. The desprayers receive the processed packets from the packet processors and transmit the packets on at least one outgoing packet stream based on the routing information. | 09-29-2011 |
20120057597 | IN-LINE PACKET PROCESSING - A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router. | 03-08-2012 |
20120219001 | SEPARATION OF DATA AND CONTROL IN A SWITCHING DEVICE - A method and apparatus for switching a data packet between a source and destination in a network. The data packet includes a header portion and a data portion. The header portion includes routing information for the data packet. The method includes defining a data path in the router comprising a path through the router along which the data portion of the data packet travels and defining a control path comprising a path through the router along which routing information from the header portion travels. The method includes separating the data path and control path in the router such that the routing information can be separated from the data portion allowing for the separate processing of each in the router. The data portion can be stored in a global memory while routing decisions are made on the routing information in the control path. | 08-30-2012 |
20130215886 | MEMORY ORGANIZATION IN A NETWORK DEVICE - A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking information for each data packet to allow for the extraction of the uniform portions of a data packet from distributed locations in memory in proper order after a routing determination has been made by the router. | 08-22-2013 |
Patent application number | Description | Published |
20080259849 | MACRO-DIVERSITY REGION RATE MODIFICATION - A system including a buffer to receive and store a stream of content data. A controller module may be configured to determine the macro-diversity region size based on a set of pre-selected configuration parameters including an incoming rate of the content data and to allocate at least a portion of the content data to a macro-diversity region, to monitor an amount of the content data in the buffer in accordance with the set of pre-selected configuration parameters including an incoming rate of the content data to determine whether the amount of content data falls into or out of a target range defined by a low-end value and a high-end value and to adjust the size of the macro-diversity region by one or more increments in response to changes in the amount of the content data in accordance with the target range. | 10-23-2008 |
20080259905 | BASE STATION SYNCHRONIZATION FOR A SINGLE FREQUENCY NETWORK - Methods, apparatus and systems for generating and synchronizing a macro-diversity region transmitted by base stations in a network includes a receiving module configured to receive a plurality of packets of content data. A controller module coupled to the receiving module and configured to generate a macro-diversity region data that includes at least one packet of the plurality of packets of content data, and to generate a time reference and frame offset information to indicate an offset from the time reference and to further identify a second base station transmission frame that will include the second macro-diversity region data. A communication module to communicate a macro-diversity region message that includes the macro-diversity region data and the macro-diversity region control information to a plurality of base stations, configured to synchronize the transmission of the macro-diversity region data at the plurality of base stations. | 10-23-2008 |
20110286435 | METHOD AND APPARATUS FOR A SCHEDULER FOR A MACRO-DIVERSITY PORTION OF A TRANSMISSION - A method, apparatuses, and system of broadcasting content data in a macro-diversity region of a data frame includes receiving a stream of transport packets. Selecting at least one burst size, from amongst a set of a plurality of predetermined burst sizes. Allocating one or more data bursts with the selected burst size to the macro-diversity region of the data frame, each data burst comprising at least a portion of the received transport packets and wherein the at least one burst size is selected so as to minimize a number of data bursts allocated to the macro-diversity region. Then communicating the allocation of data bursts to a transmitter that includes the allocation of data bursts in the macro-diversity region of a data frame transmitted by the transmitter. | 11-24-2011 |
20140204828 | METHOD AND APPARATUS FOR MULTICAST AND BROADCAST SERVICE MANAGEMENT - Methods, apparatuses, and systems for announcing services available in a macro-diversity region of a data frame broadcast by a plurality of base stations in a single frequency network to a plurality of subscriber stations, including providing to the client station broadcast service identification and type of service information. Other functions include data content synchronization, broadcasting and forwarding of multicast and broadcast services (MBS) packets, and MBS session control. | 07-24-2014 |
Patent application number | Description | Published |
20090168235 | ENHANCED CPP READ SENSORS WITH LATERAL SPIN TRANSPORT - CPP read sensors and associated methods of fabrication are described that provide lateral spreading of a sense current along the length of an AFM layer of the read sensor. Winged regions (i.e., extended portions) are added to the layers of a CPP sensor stack to induce lateral spreading of the sense current in the AFM layer. Particularly, the pinned layer and the AFM layer have widths greater than the other layers of the sensor stack. Further, the pinned layer comprises multiple layers of materials, with a first layer of material closer to the AFM layer having a lower conductivity and/or a lower spin dependent scattering asymmetry than the second layer of material. | 07-02-2009 |
20090168263 | READ TRANSDUCER AND MAGNETIC STORAGE SYSTEM IMPLEMENTING SAME - A transducer according to one embodiment comprises a first ferromagnetic layer; a second ferromagnetic layer; and an electrically conductive layer positioned between the ferromagnetic layers; wherein a length of the first ferromagnetic layer in a first direction parallel to a plane of deposition thereof is greater than a length of the electrically conductive layer in the first direction such that a first end of the first ferromagnetic layer extends beyond an end of the electrically conductive layer in the first direction, wherein an electrical current enters or exits the end of the first ferromagnetic layer that extends beyond the end of the electrically conductive layer in the first direction. Additional transducer structures, and systems implementing such transducers, are also disclosed. | 07-02-2009 |
20100142099 | LOW RESISTANCE TUNNEL MAGNETORESISTANCE (TMR) STRUCTURE - A magnetic structure in one embodiment includes a tunnel barrier layer; a free layer; and a buffer layer between the tunnel barrier layer and the free layer, wherein a cross sectional area of the tunnel barrier layer in a direction parallel to a plane of deposition thereof is greater than a cross sectional area of the free layer in a direction parallel to a plane of deposition thereof, wherein a cross sectional area of the buffer layer in a direction parallel to a plane of deposition thereof is greater than a cross sectional area of the free layer in the direction parallel to the plane of deposition thereof. Additional systems and methods are also presented. | 06-10-2010 |
20120164757 | Method for Junction Isolation to Reduce Junction Damage for a TMR Sensor - The present invention provides a method for manufacturing a TMR sensor that reduces damage to a sensor stack during intermediate stages of the manufacturing process. In an embodiment of the invention, after formation of a sensor stack, a protective layer is deposited on the sensor stack that provides protection from materials that may be used in subsequent steps of the manufacturing process. The protective layer is subsequently converted to an insulating layer and the thickness of the insulating layer is extended to an appropriate thickness. In converting the protective layer to an insulating layer, the sensor stack is not directly exposed to materials that may damage it. For example, in an embodiment of the invention, Mg is used as the protective layer that is subsequently converted to MgO with the introduction of oxygen. Although direct contact of oxygen with the sensor stack may cause damage to the sensor stack, direct contact is avoided by the present invention. Subsequently, the thickness of the insulating layer, in this example can be extended to an appropriate thickness without exposing the sensor stack to damage causing oxygen and inter-diffusion. | 06-28-2012 |
20140168822 | MAGNETIC SENSOR WITH EXTENDED PINNED LAYER AND PARTIAL WRAP AROUND SHIELD - A magnetic read head that has improved pinned layer stability while also maintaining excellent free layer stability. The free layer has sides that define a trackwidth of the sensor and a back edge that defines a functional stripe height of the sensor. However, the pinned layer can extend significantly beyond both the width of the free layer and the back edge (e.g. stripe height) of the free layer. The sensor also has a soft magnetic bias structure that compensates for the reduced volume presented by the side extension of the pinned layer. The soft magnetic bias structure can be magnetically coupled with the trailing magnetic shield, either parallel coupled or anti-parallel coupled. In addition, all or a portion of the soft magnetic bias structure can be exchange coupled to a layer of anti-ferromagnetic material in order to improve the robustness of the soft magnetic bias structure. | 06-19-2014 |
20140168824 | MAGNETIC SENSOR HAVING AN EXTENDED PINNED LAYER AND SHAPE ENHANCED BIAS STRUCTURE - A magnetic read sensor having an extended pinned layer structure and also having an extended free layer structure. The extended pinned layer structure and extended free layer structure both extend beyond the strip height of the free layer of the sensor to provide improved pinning strength as well as improved free layer biasing reliability and bias field strength. | 06-19-2014 |
20150062751 | MAGNETIC SENSOR HAVING AN EXTENDED PINNED LAYER WITH STITCHED ANTIFERROMAGNETIC PINNING LAYER - A magnetic sensor having a novel pinning structure resulting in a greatly reduced gap spacing. The sensor has a magnetic free layer structure that extends to a first stripe height and a magnetic pinned layer structure that extends to a second stripe height that is longer than the first stripe high. A layer of anti-ferromagnetic material is formed over the pinned layer structure in the region beyond the first stripe height location. In this way, the antiferromagnetic layer is between the pinned layer and the second or upper shield and does not contribute to gap spacing. | 03-05-2015 |
Patent application number | Description | Published |
20100291882 | SYSTEM AND METHOD FOR RESOLVING CONFLICTS BETWEEN AIR INTERFACES IN A WIRELESS COMMUNICATION SYSTEM - A device and method for resolving conflicts between air interfaces in a wireless communication system are disclosed. In one embodiment, the method comprises communicating over a first air interface, receiving a request for resources for concurrent use in communicating over a second air interface, determining that a conflict does not exist between resources for the first air interface and at least a portion of the requested resources for the second air interface, and concurrently communicating over the first air interface using resources for the first air interface and communicating over the second air interface using at least a portion of the requested resources for the second air interface. | 11-18-2010 |
20130084861 | EVOLUTION-DATA OPTIMIZED (EVDO) SESSION HANDLING DURING MOBILITY WITH SUPPORT FOR S101 SIGNALING INTERFACE - Certain aspects of the present disclosure propose techniques for Evolution-Data Optimized (EVDO) session handling during inter radio access technology (IRAT) mobility with support for S101 signaling interface. A UE may determine a mobility scenario for transfer of the UE among a first cell and a second cell, while the UE has an EVDO session. The UE may further determine whether pre-registration of a UE EVDO session is allowed via an S101 signaling interface. The UE may perform a procedure related to the EVDO session based on the determined mobility scenario and whether the pre-registration is allowed or not. | 04-04-2013 |
20130100795 | METHODS AND APPARATUS FOR HANDLING FAILURE AND RETRY MECHANISMS DURING eHRPD PRE-REGISTRATION - Aspects disclosed herein relate to effectively handling failure and retry mechanisms during pre-registration for an eHRPD optimized handover. In one example, a UE may be equipped to detect one or more instances of failure during a pre-registration procedure as part of an optimized handover process. The UE may further be equipped to perform one or more pre-registration retry processes based on the detected one or more instances of failure. In one aspect, the one or more instances of failure may include any combination of a permanent LTE connection failure, a temporary LTE connection failure, a session negotiation failure, a virtual connection failure when bringing up a data call, a link control protocol (LCP) failure, etc. | 04-25-2013 |
20130165121 | REDUCING DATA OPTIMIZED SESSION NEGOTIATION TIME AND FACILITATING ACTIVE HANDOFF - A communication entity, such as a wireless communication device, is handed off from a one network to a data optimized network. To facilitate the handoff and interruptions that may occur during the handoff, the communication entity stores data optimized session state information. The communication entity notifies the data optimized network that it is ready to be handed off to the data optimized network after the communication entity determines it is ready to be handed off. | 06-27-2013 |
20150055569 | IDENTIFYING A CHANNEL FOR NETWORK COMMUNICATION - Communication devices configured to identify a channel for network communication are disclosed. For example, an apparatus operable in a wireless communication network can receive a message that specifies a list of channels in operation in a network, remove at least one channel from the list of channels, and identify a channel from among the list of channels other than the at least one removed channel for communication with the network. The apparatus may be able to increase the likelihood that it will acquire the network, even though the network may be utilizing one or more channels that are not supported by the apparatus. Other aspects, embodiments, and features are also disclosed and claimed. | 02-26-2015 |
20150245266 | APPARATUS AND METHOD TO EXPEDITE AN INTER RADIO ACCESS TECHNOLOGY RESELECTION - Various aspects directed towards expediting an inter-RAT (radio access technology) reselection are disclosed. A user equipment (UE) operates according to a first RAT and utilizes an evolved multimedia broadcast multicast service (eMBMS) via the first RAT. A second RAT, which is unable to support eMBMS, is selected such that operation of the UE transitions from the first RAT to the second RAT. A reselection of the first RAT is then expedited by modifying at least one of a dormancy timer value initialization, a reselection timer value initialization, or a frequency priority. | 08-27-2015 |
Patent application number | Description | Published |
20140272353 | Color shift of high LSG low emissivity coating after heat treatment - Low emissivity panels can include a protection layer of silicon nitride on a layer of ZnO on a layer of Zn | 09-18-2014 |
20140272354 | Method to generate high LSG low-emissivity coating with same color after heat treatment - Low emissivity panels can include a separation layer of Zn | 09-18-2014 |
20140272395 | LOW-EMISSIVITY GLASS INCLUDING SPACER LAYERS COMPATIBLE WITH HEAT TREATMENT - Disclosed herein are systems, methods, and apparatus for forming low emissivity panels that may include a first reflective layer, a second reflective layer, and a spacer layer disposed between the first reflective layer and the second reflective layer. In some embodiments, the spacer layer may have a thickness of between about 20 nm and 90 nm. The spacer layer may include a bi-metal oxide that may include tin, and may further include one of zinc, aluminum, or magnesium. The spacer layer may have a substantially amorphous structure. Moreover, the spacer layer may have a substantially uniform composition throughout the thickness of the spacer layer. The low emissivity panel may be configured to have a color change as determined by Rg ΔE (i.e. as determined on the glass side) that is less than about 1.7 in response to an application of a heat treatment to the low emissivity panel. | 09-18-2014 |
20150191965 | Low-E Panels and Methods for Forming the Same - Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A low-e stack is formed above the transparent substrate. Each of the layers of the low-e stack are formed to have a specific thickness to tune the performance characteristics of the low-e panel. | 07-09-2015 |
20150311397 | Zinc Stannate Ohmic Contacts for P-Type Gallium Nitride - Transparent ohmic contacts to p-GaN and other high-work-function (≧4.2 eV) semiconductors are fabricated from zinc stannate (e.g., ZnSnO | 10-29-2015 |
20150345005 | Seed layer for low-e applications - Methods, and coated panels fabricated from the methods, are disclosed to form multiple coatings, (e.g., one or more infrared reflective layers), with minimal color change before and after heat treatments. For example, by adding appropriate seed layers between the IR reflective layers and the base oxide layers, the color performance can be maintained regardless of high temperature processes. The optical filler layers can include a metal oxide layer. In some embodiments, the seed layer can include nickel, titanium, and niobium, forming a nickel titanium niobium alloy such as NiTiNb. | 12-03-2015 |
20150368152 | Low-E Panels and Methods for Forming the Same - Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A reflective layer is formed above the transparent substrate. A dielectric layer is formed between the transparent substrate and the reflective layer. The dielectric layer includes niobium, tin, and aluminum. | 12-24-2015 |
20160102013 | Low-E Panels and Methods for Forming the Same - Embodiments provided herein describe low-e panels and methods for forming low-e panels. A transparent substrate is provided. A reflective layer is formed above the transparent substrate. A metal oxide layer is formed between the transparent substrate and the reflective layer. A base layer is formed between transparent substrate and the metal oxide layer. The base layer has a first refractive index. A dielectric layer is formed between the base layer and the metal oxide layer. The dielectric layer has a second refractive index. | 04-14-2016 |