Patent application number | Description | Published |
20090102994 | IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY AND METHOD FOR FABRICATING THE SAME - An in-plane switching mode liquid crystal display according to an embodiment includes gate lines arranged in a first direction on an array substrate, data lines arranged in a second direction substantially perpendicular to the first direction, one or more storage electrodes provided on the array substrate, common electrodes extending across each pixel region, pixel electrodes arranged to be substantially parallel to the common electrodes, the common electrodes and the pixel electrodes being alternately arranged to generate an in-plane field in each pixel region, thin film transistors (TFTs) provided at intersection areas of the gate lines and the data lines, each TFT including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode and a gate electrode, and at least one common line located under the respective common electrode in the pixel region, the common line being substantially parallel to the data lines. | 04-23-2009 |
20090104725 | Liquid crystal display device and method for manufacturing the same - A liquid crystal display device includes first and second substrates bonded to each other, first column spacers on the first substrate, protrusions on the second substrate that contact a center portion of an upper surface of the spacers, respectively, recesses formed in the second substrate surrounding the protrusions, respectively, and a liquid crystal layer between the first and second substrates. | 04-23-2009 |
20130040409 | IN-PLANE SWITCHING MODE LIQUID CRYSTAL DISPLAY AND METHOD FOR FABRICATING THE SAME - A method for fabricating an in-plane switching (IPS) type liquid crystal display (LCD) device according to an embodiment includes forming gate lines arranged in a first direction and data lines arranged in a second direction substantially perpendicular to the first direction, the gate lines and the data lines defining pixel regions on an array substrate; forming a storage electrode on the array substrate; forming common electrodes extending across each pixel region; forming pixel electrodes arranged to be substantially parallel to the common electrodes, the common electrodes and the pixel electrodes being alternately arranged to generate an in-plane field in each pixel region; and forming thin film transistors (TFTs) at intersection areas of the gate lines and the data lines, each TFT including a source electrode connected to the corresponding data line, a drain electrode connected to the corresponding pixel electrode and a gate electrode. | 02-14-2013 |