Patent application number | Description | Published |
20080217689 | SEMICONDUCTOR DEVICES HAVING SILICON-ON-INSULATOR (SOI) SUBSTRATES AND METHODS OF MANUFACTURING THE SAME - Semiconductor devices are provided including gate patterns on a substrate and isolation regions on the substrate. Insulating patterns are provided in the substrate below the gate patterns. Source/drain regions are provided in the substrate. Related methods of fabricating semiconductor devices are also provided. | 09-11-2008 |
20080248628 | Methods of Forming Integrated Circuit Devices Having Single Crystal Semiconductor FIN Structures that Function as Device Active Regions - Methods of forming integrated circuit devices include forming an electrically insulating layer having a semiconductor fin structure extending therethrough. This semiconductor fin structure may include at least one amorphous and/or polycrystalline semiconductor region therein. The at least one amorphous and/or polycrystalline semiconductor region within the semiconductor fin structure is then converted into a single crystalline semiconductor region. This semiconductor fin structure is then used as an active region of a semiconductor device. | 10-09-2008 |
20080293224 | METHOD OF FORMING A DIODE AND METHOD OF MANUFACTURING A PHASE-CHANGE MEMORY DEVICE USING THE SAME - In a method of forming a diode, a first amorphous thin film doped with first impurities is formed on a single crystalline substrate. A second amorphous thin film doped with second impurities is formed on the first amorphous thin film. A laser beam having sufficient energy to melt both of the first and second amorphous thin films is irradiated on the first and second amorphous thin films to change crystal structures of the first and second amorphous thin films using the single crystalline substrate as a seed, so that first and second single crystalline thin films are sequentially formed on the single crystalline substrate. | 11-27-2008 |
20080308845 | Heterogeneous Group IV Semiconductor Substrates - Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized. | 12-18-2008 |
20090104759 | Methods of manufacturing semiconductor devices including a doped silicon layer - Methods for manufacturing a semiconductor device include forming a seed layer containing a silicon material on a substrate. An amorphous silicon layer containing amorphous silicon material is formed on the seed layer. The amorphous silicon layer is doped with an impurity. A laser beam is irradiated onto the amorphous silicon layer to produce a phase change of the amorphous silicon layer and change the amorphous silicon layer into a single-crystal silicon layer based on the seed layer. | 04-23-2009 |
20090130826 | Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer - A method of forming a semiconductor device having a strained silicon (Si) layer on a silicon germanium (SiGe) layer is provided. The method includes preparing a silicon substrate. A SiGe layer is formed on the silicon substrate. At least a part of the SiGe layer has a first dislocation density. A strained Si layer having a second dislocation density lower than the first dislocation density is formed on the SiGe layer. | 05-21-2009 |
20090221133 | Methods of Fabricating Silicon on Insulator (SOI) Wafers - Methods of fabricating SOI wafers are provided including providing a donor wafer and forming a hydrogen ion implantation layer in the donor wafer. A circumference portion of one side of the donor wafer is recessed to form a height difference. The one side of the donor wafer and a handle wafer are bonded to form a bonded wafer. The bonded wafer is heat treated to separate the bonded wafer along the hydrogen ion implantation layer. | 09-03-2009 |
20100109164 | STACKED INTEGRATED CIRCUIT PACKAGE FABRICATION METHODS THAT USE VIAS FORMED AND FILLED AFTER STACKING, AND RELATED STACKED INTEGRATED CIRCUIT PACKAGE STRUCTURES - Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages arc also described. | 05-06-2010 |
20100159689 | SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate. | 06-24-2010 |
20100330753 | METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES INCLUDING A TRANSCRIPTION-PREVENTING PATTERN - Integrated circuit devices are provided including a first single-crystalline layer and an insulating layer pattern on the first single-crystalline layer. The insulating layer pattern has an opening therein that partially exposes the first single-crystalline layer. A seed layer is in the opening. A second single-crystalline layer is on the insulating layer pattern and the seed layer. The second single-crystalline layer has a crystalline structure substantially the same as that of the seed layer. A transcription-preventing pattern is on the second single-crystalline layer and a third single-crystalline layer on the transcription-preventing pattern and the second single-crystalline layer. The transcription-preventing pattern is configured to limit transcription of defective portions in the second single-crystalline layer into the third single-crystalline layer. | 12-30-2010 |
20110300704 | SEMICONDUCTOR DEVICES HAVING CONTACT PLUGS WITH STRESS BUFFER SPACERS AND METHODS OF FABRICATING THE SAME - A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate. | 12-08-2011 |
20120119383 | STACKED INTEGRATED CIRCUIT PACKAGE FABRICATION METHODS THAT USE VIAS FORMED AND FILLED AFTER STACKING, AND RELATED STACKED INTEGRATED CIRCUIT PACKAGE STRUCTURES - Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described. | 05-17-2012 |
20140336228 | PHARMACEUTICAL COMPOSITION FOR PREVENTING OR TREATING HYPERTRIGLYCERIDEMIA OR HYPERTRIGLYCERIDEMIA-ASSOCIATED DISEASES - Provided is a pharmaceutical composition for preventing or treating hyperlipidemia comprising (4S,5R)-5-[3,5-bis(trifluoromethyl)phenyl]-3-({2-[4-fluoro-2-methoxy-5-(propan-2-yl)phenyl]-5-(trifluoromethyl)phenyl}methyl)-4-methyl-1,3-oxazolidin-2-one or its pharmaceutically acceptable salt; and a calcium channel blocker or a fibrate as active ingredients. | 11-13-2014 |
20140336229 | PHARMACEUTICAL COMPOSITION FOR PREVENTING OR TREATING HYPERLIPIDEMIA - Provided is a pharmaceutical composition for preventing or treating hyperlipidemia comprising (4S,5R)-5-[3,5-bis(trifluoromethyl)phenyl]-3-({2-[4-fluoro-2-methoxy-5-(propan-2-yl)phenyl]-5-(trifluoromethyl)phenyl}methyl)-4-methyl-1,3-oxazolidin-2-one or its pharmaceutically acceptable salt; and an angiotensin II receptor blocker as active ingredients. | 11-13-2014 |